THS4552 Datasheet, PDF (9/71 Pages) Texas Instruments – Dual-Channel, Low-Noise, Precision, 150-MHz, Fully Differential Amplifier

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THS4552
SBOS831 – DECEMBER 2016
7.6 Electrical Characteristics: (V_S+) – (V_S–) = 3 V
at T_A ≈ 25°C, VOCM pin = open, R_F = 1 kΩ, R_L = 1 kΩ, V_OUT = 2 V_PP, 50-Ω input match, G = 1 V/V, PD = V_S+, single-ended
input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted);
specifications are per channel; see Figure 61 for a gain of 1-V/V test circuit
PARAMETER
TEST CONDITIONS
TEST
MIN
TYP
MAX UNIT _LEVEL(1)
AC PERFORMANCE
SSBW
GPB
LSBW
SR
t_R, t_F
t_SETTLE
HD2
HD3
Small-signal bandwidth
Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
Slew rate⁽²⁾
Rise and fall time
Settling time
Overshoot and undershoot
Second-order harmonic distortion
Third-order harmonic distortion
Input voltage noise
V_OUT = 20 mV_PP, G = 1, peaking (< 1.0 dB)
V_OUT = 20 mV_PP, G = 2
V_OUT = 20 mV_PP, G = 10
V_OUT = 20 mV_PP, G = 100
V_OUT = 1 V_PP, G = 1
V_OUT = 1 V_PP, G = 1
V_OUT = 1 V_PP, FPBW, G = 1
V_OUT = 0.5-V step, G = 1, input t_R = 4 ns
To 0.1%, V_OUT = 0.5-V step, input t_R = 4 ns, G = 1
To 0.01%, V_OUT = 0.5-V step, input t_R = 4 ns, G = 1
V_OUT = 0.5-V step, G = 1, input t_R = 4 ns
f = 100 kHz, V_OUT = 2 V_PP, G = 1, R_L = 1 kΩ
f = 100 kHz, V_OUT = 4 V_PP, G = 1, R_L = 1 kΩ
f = 100 kHz, V_OUT = 2 V_PP, G = 1, R_L = 1 kΩ
f = 100 kHz, V_OUT = 4 V_PP, G = 1, R_L = 1 kΩ
f > 500 Hz, 1/f < 150 Hz
150
80
14
130
45
14
110
7.0
35
55
7%
–128
–127
–139
–125
3.4
C
MHz
C
C
MHz
C
MHz
C
MHz
C
V/µs
C
ns
C
C
ns
C
C
C
dBc
C
C
dBc
C
nV/√Hz
C
Input current noise
f > 20 kHz, 1/f < 10 kHz
0.5
pA/√Hz
C
Overdrive recovery time
G = 2, 2X output overdrive, dc coupled
100
ns
C
Closed-loop output impedance
f = 100 kHz (differential), G = 1
0.02
Ω
C
Channel-to-channel crosstalk
DC PERFORMANCE⁽³⁾
2-V_PP output on one channel, 1 MHz
–80
dBc
C
A_OL
Open-loop voltage gain
±2-V differential to 1-kΩ differential load
T_A = 25°C
V_IO
Input-referred offset voltage
T_A = 0°C to +70°C
T_A = –40°C to +85°C
Input offset voltage drift⁽⁴⁾
T_A = –40°C to +125°C
T_A = –40°C to +125°C (PW package)
Channel-to-channel input offset
voltage mismatch
T_A = 25°C (PW package)
100
–175
–225
–295
–295
–2.0
–250
120
±40
±0.45
dB
A
175
A
265
B
µV
295
B
375
B
2.0 µV/°C
B
250 µV
A
Input offset voltage drift mismatch T_A = –40°C to +125°C (PW package)
T_A = 25°C
I_IB
Input bias current
(positive current out-of-node)
T_A = 0°C to +70°C
T_A = –40°C to +85°C
Input bias current drift⁽⁴⁾
T_A = –40°C to +125°C
T_A = –40°C to +125°C
–2.6
2.6 µV/°C
B
0.35
1.0
1.5
A
0.42
1.73
B
µA
0.22
1.80
B
0.22
2.0
B
2
3.3
5.5 nA/°C
B
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at T_A ≈ 25°C. (B) Not tested in production; limits set by
characterization and simulation. (C) Typical value only for information.
(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (V_PP / √2) × 2π × f_–3dB.
(3) Currents out of pin are treated as a positive polarity.
(4) Input offset voltage drift, input bias current drift, and input offset current drift are the mean ±1-sigma values calculated by taking
measurements at the maximum-range ambient temperature end points, computing the difference, and dividing by the temperature
range. Maximum drift specifications are set by mean ±4 σ on the device distributions tested over a –40°̊C to +125°̊C ambient
temperature range. Drift is not specified by final ATE testing or QA sample test.
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