THS4552 Datasheet, PDF (51/71 Pages) Texas Instruments – Dual-Channel, Low-Noise, Precision, 150-MHz, Fully Differential Amplifier

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THS4552
SBOS831 – DECEMBER 2016
Typical Applications (continued)
10.2.1.1 Design Requirements
The requirements for this application are:
• Single-ended to differential conversion
• Attenuation by 0.2-V/V gain
• Active filter set to a Butterworth, 100-kHz response shape
• Output RC elements set by SAR input requirements (not part of the filter design)
• Filter element resistors and capacitors are set to limit added noise over the THS4552 and noise peaking
10.2.1.2 Detailed Design Procedure
The design proceeds using the techniques and tools suggested in the Design Methodology for MFB Filters in
ADC Interface Applications application note (SBOA114). The process includes:
• Scale the resistor values to not meaningfully contribute to the output noise produced by the THS4552 by itself
• Select the RC ratios to hit the filter targets when reducing the noise gain peaking within the filter design
• Set the output resistor to 10 Ω into a 2.2-nF differential capacitor
• Add 100-pF common-mode capacitors to the load capacitor to improve common noise filtering
• Inside the loop, add 20-Ω output resistors after the filter feedback capacitor to increase the isolation to the
load capacitor
• Include a place for a differential input capacitor (illustrated as 100 fF in Figure 90)
10.2.1.3 Application Curves
Probing the response to the output pins by using the THS4552 SBOC471 TINA-TI™ simulation model (before
the RC filter to the SAR ADC) illustrates the expected response plus some peaking at higher frequencies. Any
signal or noise peaking that appears at the output because of this peaking is rolled off by the RC filter between
the FDA and SAR inputs. A place for a differential input capacitor is illustrated in Figure 90 (as 0.1 pF) but is not
used for this simulation. This slight peaking is a combination of low phase margin and feedthrough via the
feedback capacitor to the increasing open-loop output impedance of Figure 68. The loop gain and phase
response are available as a TINA-TI™ simulation file.
Obtaining the SNR to the ADC input pins, and assuming an 8-V_PP full scale (2.83 V_RMS), gives the result of
Figure 92. The 113-dB SNR shown in Figure 92 does not limit the performance for any SAR application.
0
450
Gain (dB)
T _150.00
-20
Phase (deg) ₃₀₀
-40
150
140.00
-60
0
-80
-150
130.00
-100
-120
-300
120.00
-450
-140
-600
10k
100k
1M
10M
100M
Frequency (Hz)
D072
Figure 91. Gain and Phase Plot for a 100-kHz Butterworth
Filter
110.00
10k
100k
1MEG
10MEG
Frequency (Hz)
Figure 92. Signal-to-Noise Ratio Plot
100MEG
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