THS4552 Datasheet, PDF (58/71 Pages) Texas Instruments – Dual-Channel, Low-Noise, Precision, 150-MHz, Fully Differential Amplifier

THS4552
SBOS831 – DECEMBER 2016
www.ti.com
11.1 Thermal Analysis
The very low internal quiescent power dissipation for the THS4552, combined with the excellent thermal
impedance of the 24-pin VQFN package (RTW), limits the possibility of excessively high internal junction
temperatures.
To estimate the internal T_J, an estimate of the maximum internal power dissipation is first required. There are two
pieces to the internal power dissipation: quiescent current power and the power used in the output stage to
deliver load current. To simplify the latter, the worst-case output stage power drives a dc differential voltage
across a load using half the total supply voltage. Also assume a maximum ambient temperature of 125°C, giving
the maximum quiescent current as shown in Figure 98. As an example:
• Assume a maximum operating supply voltage of 5.4 V. This 5.4-V supply with a maximum I_CC of 1.46
mA/channel gives a quiescent power term of 2 × 1.46 mA × 5.4 V = 15.77 mW.
• Assume a 200-Ω differential load with a static 2.7-V differential voltage established across the load for both
channels. The 1.35 mA of dc load current generates a maximum output stage power of (5.4 V – 2.7 V) × 1.35
mA = 3.65 mW/channel and a total power dissipation of 7.3 mW for both channels.
• From the worst-case total internal P_D of 23.07 mW, multiplying the internal P_D with a 46°C/W thermal
impedance for the 24-pin VQFN package results in a 1.06°C rise from ambient.
Even for this extreme condition and the maximum-rated ambient of 125°C, the junction temperature is a
maximum of 126°C, which is less than the rated absolute maximum of 150°C. Follow this same calculation
sequence for the exact application and package selected to predict the maximum T_J.
12 Layout
12.1 Layout Guidelines
12.1.1 Board Layout Recommendations
Similar to all high-speed devices, best system performance is achieved with close attention to board layout. The
THS4552PW Evaluation Module (SLOU465) shows a good example of high-frequency layout techniques as a
reference. This EVM includes numerous extra elements and features for characterization purposes that may not
apply to some applications. General high-speed signal path layout suggestions include:
• Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs;
however, both ground and power planes must be opened up around the capacitive sensitive input and output
device pins. When the signal goes to a resistor, parasitic capacitance becomes more of a band-limiting issue
and less of a stability issue.
• Good high-frequency decoupling capacitors (0.1 µF) are required to a ground plane at the device power pins.
Additional higher-value capacitors (2.2 µF) are also required but can be placed further from the device power
pins and shared among devices. For best high-frequency decoupling, consider X2Y supply decoupling
capacitors that offer a much higher self-resonance frequency over standard capacitors.
• Differential signal routing over any appreciable distance must use microstrip layout techniques with matched
impedance traces.
• Higher-speed FDAs such as the THS4552 include a duplicate of the output pins on the input feedback side of
the larger 24-pin VQFN (RTW) package. This feature is intended to allow the external feedback resistors to
be connected with virtually no trace length on the input side of the package. This internal feedback trace also
provides a second feedback path for connecting a feedback capacitor on the input pin sides for band-limited
or multiple feedback filter designs. This internal trace shows an approximate 3.3-Ω series resistance that must
be considered in any design using that path. The TINA-TI™ model does not include that element (to be
generally applicable to all package styles) and must be added externally if the RTW package is used. Use
this layout approach without extra trace length on the critical feedback path.
• The input summing junctions are very sensitive to parasitic capacitance. Any R_G elements must connect into
the summing junction with minimal trace length to the device pin side of the resistor. The other side of the R_G
elements can have more trace length if needed to the source or to GND.
58
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