THS4552 Datasheet, PDF (32/71 Pages) Texas Instruments – Dual-Channel, Low-Noise, Precision, 150-MHz, Fully Differential Amplifier

THS4552
SBOS831 – DECEMBER 2016
www.ti.com
Taking a more complex example by using the THS4552 to attenuate a large bipolar input signal in a dc-coupled
design for an ADC is shown in Figure 71. To remove the peaking for this low-noise gain design, the two C_F
elements and an input capacitor are added to shape the noise gain at high frequencies to a capacitive divider, as
described in the Designing Attenuators section. In this example (including the 1.2-pF internal differential capacitor
at the inputs and the 0.6-pF internal feedback capacitors), the high-frequency noise gain is 3 V/V and a flat
frequency response with approximately 45 MHz of –3-dB BW is delivered.
10 k
+
4.096 V
10 k
±
VOCM
1 µF
Gain of 0.2 V/V,
DC-Coupled,
Single-Ended Source to
Differential Output
RG1
4.99 k
VS+
5V ⁺
±
VS-
0V ⁺
±
VS = ±18 V
VOCM
2.6 pF
RG2
4.99 k
3.1 pF
RF1
1k
VS+
THS4552 Wideband,
Fully Differential Amplifier
VOUT = 7.2 VPP
Differential
±
+
FDA
±
+
PD
VS- ^VS+
RF2
1k
RL
A 1-k load is very
1 k ^{important to include because}
of high-frequency resonance;
no load may oscillate.
For Attenuator Design:
NG1 = 1.2
NG2 = 3
GBP = 135 MHz
Zo = 14.3 MHz
3.1 pF
Copyright © 2016, Texas Instruments Incorporated
Figure 71. DC-Coupled, Single-Ended to Differential Attenuator Design
In this example, the output V_OCM is 4.096 V / 2, which equals 2.048 V and the source signal V_CM is 0 V. These
values set the nominal input pin V_ICM to 2.048 V × 4.99 kΩ / (4.99 kΩ + 1 kΩ) = 1.71 V. Applying a ±18-V input at
the 4.99-kΩ input resistor produces a 7.2-V_PP differential output. That is, a ±1.8-V swing on the lower output side
around the 2.048-V common-mode voltage. This 0.248-V to 3.84-V relative-to-ground swing at the output is well
within the 0.2-V output headrooms to the 0-V to 5-V supplies used in the example in Figure 71 (with the same
swing inverted on the other output side). That output swing on the lower side produces an attenuated input
common mode swing of (±1.8 V × (4.99 kΩ / (4.99 kΩ + 1 kΩ)) = ±1.5 V around the midscale input bias of 1.71
V. This 0.2-V to 3.2-V input common-mode swing is well within the available 0-V to 3.8-V input range. This ±18-V
bipolar input signal is delivered to a SAR ADC with a 7.2-V_PP differential output with all I/O nodes operating in
range using a single 5-V supply design. The source must sink the 2.048 V / 5.99 kΩ = 0.34-mA common-mode
level-shifting current to take the input 0-V common-mode voltage up to the midscale 1.71-V V_ICM operating
voltage. Using the single-ended input impedance of Equation 4, the source must also drive an apparent input
load of 5.44 kΩ.
Most designs do not run into an input range limit. However, using the approach shown in this section can allow a
quick assessment of the input V_ICM range under the intended full-scale output condition. The TINA-TI™
simulation file for Figure 71 can be used to plot the input voltages under the intended swings and application
circuit to verify that there is no limiting from this effect. Driving the I/O nodes out of range in the TINA-TI™ model
results in convergence problems. Increasing the positive and negative supplies slightly in simulation is an easy
way to discover the simulated swings that might be going out of range.
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