THS4552 Datasheet, PDF (7/71 Pages) Texas Instruments – Dual-Channel, Low-Noise, Precision, 150-MHz, Fully Differential Amplifier

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THS4552
SBOS831 – DECEMBER 2016
Electrical Characteristics: (V_S+) – (V_S–) = 5 V (continued)
at T_A ≈ 25°C, VOCM pin = open, R_F = 1 kΩ, R_L = 1 kΩ, V_OUT = 2 V_PP, 50-Ω input match, G = 1 V/V, PD = V_S+, single-ended
input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise noted);
specifications are per channel; see Figure 61 for a gain of 1-V/V test circuit
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
TEST
LEVEL ⁽¹⁾
DC PERFORMANCE (continued)
I_OS
Input offset current
INPUT
Input offset current mismatch
Input offset current drift⁽⁴⁾
Offset current drift mismatch
T_A = 25°C
T_A = 0°C to +70°C
T_A = –40°C to +85°C
T_A = –40°C to +125°C
T_A = 25°C
T_A = –40°C to +125°C (PW package)
T_A = –40°C to +125°C (PW package)
–50
±10
50
A
–57
63
B
nA
–68
67
B
–68
78
B
–65
65 nA
D
–240
±20
240 pA/°C
B
–260
±20
260 pA/°C
B
Common-mode input, low
> 90-dB CMRR at input
range limits
T_A = 25°C
T_A = –40°C to +125°C
(V_S–) – 0.2 (V_S–) – 0.1
V
A
(V_S–) – 0.1
V_S–
B
Common-mode input, high
> 90-dB CMRR at input
range limits
T_A = 25°C
(V_S+) – 1.2 (V_S+) – 1.1
T_A = –40°C to +125°C (V_S+) – 1.3 (V_S+) – 1.2
A
V
B
CMRR Common-mode rejection ratio
Input pins at [(V_S+) – (V_S–)] / 2
93
110
dB
A
Input impedance differential mode Input pins at [(V_S+) – (V_S–)] / 2
100 || 1.2
kΩ || pF
C
OUTPUT
Output voltage, low
T_A = 25°C
T_A = –40°C to +125°C
(V_S–) + 0.2
(V_S–) +
0.23
A
V
(V_S–) + 0.2
(V_S–) +
0.22
B
Output voltage, high
T_A = 25°C
T_A = –40°C to +125°C
(V_S+) –
0.23
(V_S+) – 0.2
(V_S+) –
0.22
(V_S+) – 0.2
A
V
B
Continuous output current
Linear output current
POWER SUPPLY
T_A = 25°C, ±2.5 V, R_L= 40 Ω,
V_OCM offset < ±20 mV
T_A = –40°C to +125°C, ±2.1 V, R_L= 40 Ω,
V_OCM offset < ±20 mV
T_A = 25°C, ±2.1 V, R_L= 50 Ω, A_OL > 80 dB
T_A = –40°C to +125°C, ±1.6 V, R_L= 50 Ω,
A_OL > 80 dB
±60
±65
±50
±40
±45
±30
A
mA
B
A
mA
B
Specified operating voltage
I_Q
Quiescent operating current per
channel
T_A ≈ 25°C⁽⁵⁾, V_S+ = 5 V
T_A = –40°C to +125°C, V_S+ = 5 V
Supply current at maximum
operating supply per channel
T_A = 25°C, V_S+ = 5.4 V
2.7
5
5.4 V
B
1.28
1.37
1.44
A
mA
0.97
1.92
B
1.33
1.36
1.46 mA
D
dI_Q/dT
Quiescent current temperature
coefficient per channel
V_S+ = 5 V
2.4
3.9
5.4 µA/°C
B
±PSRR Power-supply rejection ratio
POWER-DOWN
Either supply pin to differential V_OUT
93
110
dB
A
Enable voltage threshold
Specified on above (V_S–) + 1.15 V
(V_S–) + 1.15
V
A
Disable voltage threshold
Specified off below (V_S–) + 0.55 V
(V_S–) + 0.55
V
A
Disable pin bias current
PD = V_S– → V_S+
–100
±10
100 nA
A
Power-down quiescent current
Disable logic at (V_S–) + 0.55 V
Disable logic at (V_S–)
–2
1
5
A
µA
–2
1
5
A
t_ON
Turn-on time delay
Time from PD = low to V_OUT = 90% of final value
700
ns
C
t_OFF
Turn-off time delay
Time from PD = low to V_OUT = 10% of final value
100
ns
C
(5) T_A = 25°C and I_CC ≈ 1.37 mA. The test limit is expanded for the ATE ambient range of 22°C to 32°C with a 4-µA/°C I_CC temperature
coefficient considered; see Figure 98.
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