THS4552 Datasheet, PDF (23/71 Pages) Texas Instruments – Dual-Channel, Low-Noise, Precision, 150-MHz, Fully Differential Amplifier

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THS4552
SBOS831 – DECEMBER 2016
Example Characterization Circuits (continued)
The frequency domain characterization curves start with the selections of Figure 61. Some of the features in this
test circuit include:
• The elements on the non-signal input side exactly match the signal-side input resistors. This feature has the
effect of more closely matching the divider networks on each side of the FDA. The three resistors on the non-
signal input side can be replaced by a single resistor to ground using a standard E96 value of 1.02 kΩ with
some loss in gain balancing between the two sides; see the Output DC Error and Drift Calculations and the
Effect of Resistor Imbalances section).
• Translating from a 1-kΩ differential load to a 50-Ω environment introduces considerable insertion loss in the
measurements (–31.8 dB in Figure 61). The measurement path insertion loss is normalized out when
reporting the frequency response curves to show the gain response to the FDA output pins.
• In the pass band for the output balun, the network analyzer 50-Ω load reflects to be in parallel with the 52.3-Ω
shunt termination. These elements combine to show a differential 1-kΩ load at the output pins of the
THS4552. The source impedance presented to the balun is a differential 50-Ω source. Figure 62 and
Figure 63 show the TINA-TI™ model (available as a TINA-TI™ simulation file) and resulting response
flatness for this relatively low-frequency balun providing 0.1-dB flatness through 100 MHz.
L1's Inductance : 198.94 uH
L2's Inductance : 198.94 uH
Mutual Inductance : 198.92972 uH
R1 25 ADTL1-4-75 Model 198.94u
VG1
R2 25
+
V
VM1
Figure 62. Output Measurement Balun Simulation Circuit in TINA-TI™
-6
10
-6.01
8
-6.02
6
-6.03
4
-6.04
2
-6.05
0
-6.06
-2
-6.07
-4
-6.08
-6.09
-6.1
1k
Gain (dB)
Phase (deg)
10k
100k
1M
Frequency (Hz)
10M
-6
-8
-10
100M
D061
Figure 63. Output Measurement Balun Flatness Test
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