THS4552 Datasheet, PDF (5/71 Pages) Texas Instruments – Dual-Channel, Low-Noise, Precision, 150-MHz, Fully Differential Amplifier

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THS4552
SBOS831 – DECEMBER 2016
7.2 ESD Ratings
A. THS4552 in PW Pacakges
V_(ESD) Electrostatic discharge
B. THS4552 in RTW Package
V_(ESD) Electrostatic discharge
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾
±2500
±1250
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾⁽³⁾
Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾
±1000
±1250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) ESD limit of ±1000 V for any pin to thermal pad. Pin-to-pin HBM ESD specifications are rated at ±2500 V.
UNIT
V
V
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
V_S+
Single-supply positive voltage
T_A
Ambient temperature
MIN
NOM
MAX UNIT
2.7
5
5.4
V
–40
25
125
°C
7.4 Thermal Information
THERMAL METRIC⁽¹⁾
THS4552
RTW ⁽²⁾
(VQFN)
PW
(TSSOP)
UNIT
24 PINS
16 PINS
R_θJA
R_θJC(top)
R_θJB
ψ_JT
ψ_JB
R_θJC(bot)
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
46.0
117.2
°C/W
34.6
48.8
°C/W
19.7
70.2
°C/W
10.0
21.1
°C/W
19.7
69.8
°C/W
12.9
N/A
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Thermal impedance for RTW reported with backside thermal pad soldered to heat spreading plane.
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