THS4552 Datasheet, PDF (42/71 Pages) Texas Instruments – Dual-Channel, Low-Noise, Precision, 150-MHz, Fully Differential Amplifier

THS4552
SBOS831 – DECEMBER 2016
www.ti.com
Application Information (continued)
Table 4. Swept Gain of the Output- and Input-Referred Spot Noise Calculations
GAIN (V/V)
0.1
1
2
5
10
R_F (Ω)
1000
1000
1020
1000
1020
R_G1 (Ω)
10000
976
499
187
88.7
R_T (Ω)
49.9
51.1
52.3
59
69.8
R_G2 (Ω)
10000
1000
523
215
118
Z_IN (Ω)
49.66
49.2
48.9
50.2
50.6
A_V (V/V)
0.09965
1.0096
1.988
5.057
10.09
E_O (nV/√Hz)
7
10.4
13.9
23
36.4
E_I (nV/√Hz)
70
10.4
6.95
4.6
3.64
10.1.2 Factors Influencing Harmonic Distortion
As illustrated in the swept frequency harmonic distortion plots (Figure 13 and Figure 31), the THS4552 provides
extremely low distortion at lower frequencies. In general, an FDA output harmonic distortion mainly relates to the
open-loop linearity in the output stage corrected by the loop gain at the fundamental frequency. When the total
load impedance decreases, including the effect of the feedback resistor elements in parallel for loading purposes,
the output stage open-loop linearity degrades, thus increasing the harmonic distortion; see Figure 16 and
Figure 34. When the output voltage swings increase, very fine scale open-loop output stage nonlinearities
increase that also degrade the harmonic distortion; see Figure 14 and Figure 32. Conversely, decreasing the
target output voltage swings drops the distortion terms rapidly. A nominal swing of 2 V_PP is used for harmonic
distortion testing where Figure 14 illustrates the effect of going up to an 8-V_PP differential input that is more
common with SAR converters.
Increasing the noise gain functions to decrease the loop gain resulting in the increasing harmonic distortion
terms; see Figure 18 and Figure 36. One advantage to the capacitive compensation for the attenuator designs is
that the noise gain is shaped up with frequency to achieve a crossover at an acceptable phase margin at higher
frequencies. This technique (see the Designing Attenuators section) holds the loop gain high at frequencies
lower than the noise gain zero, thus improving distortion at lower frequencies.
The THS4552 holds nearly constant distortion when the V_OCM operating point is moved in the allowed range; see
Figure 17 and Figure 35. Clipping into the supplies with any combination of V_OCM and V_OPP rapidly degrades
distortion performance.
The THS4552 does an exceptional job of converting from single-ended inputs to differential outputs with very low
harmonic distortions. External resistors of 1% tolerance are used in characterization with good results.
Unbalancing the feedback divider ratios does not degrade distortion directly. Imbalanced feedback ratios convert
common-mode inputs to a differential mode at the outputs with the gain described in the Output DC Error and
Drift Calculations and the Effect of Resistor Imbalances section.
10.1.3 Driving Capacitive Loads
The capacitive load of an ADC or some other next-stage device is commonly required to be driven. Directly
connecting a capacitive load to the output pins of a closed-loop amplifier such as the THS4552 can lead to an
unstable response; see the step response plots into a capacitive load (Figure 8, Figure 10, Figure 26, and
Figure 28). One typical remedy to this instability is to add two small series resistors (R_O) at the outputs of the
THS4552 before the capacitive load. Figure 6 and Figure 24 illustrate parametric plots of recommended R_O
values versus differential capacitor load values and gains. Operating at higher noise gains requires lower R_O
values to obtain a ±0.5-dB flat response for the same capacitive load. Some direct parasitic loading is acceptable
without a series R_O that increases with gain setting (see Figure 8, Figure 10, Figure 26, and Figure 28 where the
R_O value is 0 Ω). Even when these plots suggest that a series R_O is not required, good practice is to leave a
place for the R_O elements in a board layout (a 0-Ω value initially) for later adjustment in case the response
appears unacceptable.
The rail-to-rail output stage of the THS4552 has an inductive characteristic in the open-loop output impedance at
higher frequencies; see Figure 68. This inductive open-loop output impedance introduces added phase shift at
the output pins for direct capacitive loads and feedback capacitors. Larger values of feedback capacitors (greater
than 100 pF) can risk a low phase margin. Including a 10-Ω to 15-Ω series resistor with a feedback capacitor can
be used to reduce this effect.
The TINA-TI™ simulation model does a good job of predicting these issues and illustrating the effect for different
choices of capacitive load isolating resistors (R_O) and different feedback capacitor configurations.
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