DS92LV1260_14 Datasheet, PDF (9/21 Pages) Texas Instruments – Six Channel 10 Bit BLVDS Deserializer

DS92LV1260
www.ti.com
SNLS134F – DECEMBER 2000 – REVISED APRIL 2013
Step 1: After applying power to the Deserializer, the outputs are held in TRI-STATE and the on-chip power-
sequencing circuitry disables the internal circuits. When V_cc reaches V_ccOK (2.1V), the PLL in each deserializer
begins locking to the local clock (REFCLK). A local on-board oscillator or other source provides the specified
clock input to the REFCLK pin.
Step 2: The Deserializer PLL must synchronize to the Serializer to complete the initialization. Refer to the
Serializer data sheet for the proper operation during this step of the Initialization State. The Deserializer identifies
the rising clock edge in a synchronization pattern or random data and after 80 clock cycles will synchronize to the
data stream from the serializer. At the point where the Deserializer's PLL locks to the embedded clock, the
LOCKn pin goes low and valid data appears on the output. Note that this differs from pervious deserializers
where the LOCKn signal was not synchronous to valid data appearing on the outputs.
Data Transfer
After initialization, the serializer transfers data to the deserializers. The serial data stream includes a start and
stop bit appended by the serializer, which frame the ten data bits. The start bit is always high and the stop bit is
always low. The start and stop bits also function as clock bits embedded in the serial stream.
The Serializer transmits the data and clock bits (10+2 bits) at 12 times the TCLK frequency. For example, if
TCLK is 40 MHz, the serial rate is 40 X 12 = 480 Mbps. Since only 10 bits are from input data, the serial
'payload' rate is 10 times the TCLK frequency. For instance, if TCLK = 40 MHz, the payload data is 40 X 10 =
400 Mbps. TCLK is provided by the data source and must be in the range 20 MHz to 40 MHz nominal.
When one of six Deserializer channels synchronizes to the input from a Serializer, it drives its LOCKn pin low
and synchronously delivers valid data on the output. The Deserializer locks to the embedded clock, uses it to
generate multiple internal data strobes, and drives the embedded clock to the RCLKn pin. The RCLKn is
synchronous to the data on the ROUT[n0:n9] pins. While LOCKn is low, data on ROUT [n0:n9] is valid.
Otherwise, ROUT[n0:n9] is invalid.
All ROUT, LOCK, and RCLK signals will drive a minimum of three CMOS input gates (15pF load) with a 40 MHz
clock. This amount of drive allows bussing outputs of two Deserializers and a destination ASIC. REN controls
TRI-STATE of all the outputs.
The Deserializer input pins are high impedance during Powerdown (PWRDN low) and power-off (V_cc = 0V).
Resynchronization
Whenever one of the six Deserializers loses lock, it will automatically try to resynchronize. For example, if the
embedded clock edge is not detected two times in succession, the PLL loses lock and the LOCKn pin is driven
high. The system must monitor the LOCKn pin to determine when data is valid.
The user has the choice of allowing the deserializer to re-synch to the data stream or to force synchronization by
pulsing the Serializer SYNC1 or SYNC2 pin. This scheme is left up to the user discretion. One recommendation
is to provide a feedback loop using the LOCKn pin itself to control the sync request of the Serializer (SYNC1 or
SYNC2). Dual SYNC pins are given for multiple control in a multi-drop application.
Powerdown
The Powerdown state is a low power sleep mode that the Serializer and Deserializer typically occupy while
waiting for initialization, or to reduce power consumption when no data is transfers. The Deserializer enters
Powerdown when PWRDN is driven low. In Powerdown, the PLL stops and the outputs go into TRI-STATE,
which reduces supply current to the microamp range. To exit Powerdown, the system drives PWRDN high.
Upon exiting Powerdown, the Deserializer enters the Initialization state. The system must then allow time to
Initialize before data transfer can begin.
TRI-STATE
When the system drives REN pin low, the Deserializer enters TRI-STATE. This will TRI-STATE the receiver
output pins (ROUT[00:59]) and RCLK[0:5]. When the system drives REN high, the Deserializer will return to the
previous state as long as all other control pins remain static (PWRDN, RCLK_R/F).
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