DS92LV1260_14 Datasheet, PDF (15/21 Pages) Texas Instruments – Six Channel 10 Bit BLVDS Deserializer

DS92LV1260
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B2,B14
Pin No.
C12,C13,B13
Pin Name
GND
SEL (0:2)
A4-A3, C6-C5, A7-A6, C9-C8,
A10-A9, C11-C10, A13-A12
D12
F12
B12,A14,D10
B11
C7
B9
A11
B7
A8
B8
A5
B6
D7
Rin(n) +/-
PVdd
AVdd
PGND
AGND
AVdd
AVdd
AVdd
AGND
AGND
AGND
AGND
AVdd
DGND
B5
PWRDN
C4
RCLK_R/F
A2
REN
B4
REFCLK
D5
DGND
A1
DGND
B1
N/C
D6
DVdd
B3
DVdd
C3
CHTST
F3,P1,N3,P12,P13,D13
LOCK (0:5)
E6,J5,K5,K10,J10,E9
K3, K4, H3, H4, H2, G4, G3,
F4, E4, E2, J3, L3, J2 ,L1 ,K2
,M1 ,N1 ,N2 ,M2 ,M3 ,M7 ,L6
,N6 ,M6 ,P4, M5, P3, N4, P2,
M4, M8, L8, N9, M9, L9, M10,
M11, N11, P11, N12, K13,
L12, L14, M14, L13, L11, M12,
N13, N14, P14, K12, J12, J11,
H12, H11, G11, G12, E12,
E13, E14
E5,G5,J6,K8,H9,F8
DVdd
Rout nx
DGND
SNLS134F – DECEMBER 2000 – REVISED APRIL 2013
PIN DESCRIPTIONS
Type
Description
GND GND pins for ESD structures
3.3V
CMOS
I
These pins control which Bus LVDS input is steered to the CHTST output
Bus
LVDS
I
Bus LVDS differential input pins
Supply voltage for PLL circuitry
Supply voltage for input buffer circuitry
GND pin for PLL circuitry
GND pin for input buffer circuitry
Supply voltage for LVDS REC.
Supply voltage for LVDS REC.
Supply voltage for Band Gap reference.
GND pin for AVDD.
GND pin for AVDD1.
GND pin for BGVDD.
GND pin for VDDI.
Supply voltage for input logic circuitry.
Tie to digital ground.
3.3V
CMOS
I
Controls whether the device is active or in 'sleep' mode
3.3V
CMOS
I
Controls the relation of Rout data to RCLK edge: RCLK_R/F = H setup and
hold times are referred to the rising RCLK edge; RCLK_R/F = L setup and hold
times are referenced to the falling RCLK edge.
3.3V
CMOS
I
Enables the Routn, RCLKn, and SYNCCLK outputs.
3.3V
CMOS
I
Frequency reference clock input.
GND pin for VDDO
GND for digital section.
Do not connect.
Supply voltage for digital section.
Supply voltage for digital section.
3.3V
CMOS
O
Allows low speed testing of the Rin inputs under control of the SEL (0:2) pins.
3.3V
CMOS
O
Indicates the status of the PLLs for the individual deserializers: LOCK= L
indicates locked, LOCK= H indicates unlicked.
Supply voltage for the logic circuitry.
3.3V
CMOS
O
Outputs for the ten bit deserializers, n = deserializer number, x = bit number
GND pins for digital section.
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