DS92LV1260_14 Datasheet, PDF (3/21 Pages) Texas Instruments – Six Channel 10 Bit BLVDS Deserializer

DS92LV1260
www.ti.com
SNLS134F – DECEMBER 2000 – REVISED APRIL 2013
Electrical Characteristics⁽¹⁾ (continued)
Basic functionality and specifications per deserializer channel will be similar to DS92LV1212A. Over recommended operating
supply and termperature ranges unless otherwise specified.⁽²⁾
Parameter
Test Conditions
Pin/Freq.
Min Typ Max Units
Bus LVDS DC specifications
V_TH
Differential Threshold High
Voltage
V_TL
Differential Threshold Low
Voltage
I_IN
Input Current
Supply Current
VCM = 1.1V (V_RI+-V_RI-)
V_in = +2.4V,
V_cc = 3.6 or 0V
V_in =0V,
V_cc = 3.6 or 0V
RI+, RI-
+3 +50 mV
-50
-2
mV
-10 +/- 1 +10
uA
-10 +/- 1 +10
uA
3.6V, 40 MHz,
I_CCR
Worst Case Supply Current Checker Board
Pattern, CL=15pF
460 530 mA
I_CCXR
Supply Current when Powered PWRDN= 0.8V
Down
REN = 0.8V
0.36 1
mA
Timing Requirements for REFCLK
t_RFCP
REFCLK Period
t_RFDC
REFCLK Duty Cycle
t_RFCP/t_TCP Ratio of REFCLK to TCLK
t_RFTT
REFCLK Transition Time
Deserializer Switching Characteristics
25
62.5
ns
40
50
60
%
0.95
1.05
8
ns
t_RCP
t_RDC
t_CHTST
RCLK Period
RCLK Duty Cycle
Period of Bus LVDS signal
when CHTST is selected by
MUX
See ⁽⁴⁾
RCLK
CHTST
25
62.5
ns
43
50
55
%
25
ns
t_CLH
CMOS/TTL Low-to-High
Transition Time
1.7
6
ns
t_CHL
CMOS/TTL High-to-Low
Transition Time
1.6
6
ns
t_ROS
t_ROH
t_HZR
t_LZR
t_ZHR
t_ZLR
Rout Data Valid before RCLK See Figure 3
Rout Data Valid after RCLK See Figure 3
High to TRI-STATE Delay
Low to TRI-STATE Delay
TRI-STATE to High Delay
TRI-STATE to Low Delay
t_DD
Deserializer Delay
See Figure 2
Room Temp
3.3V
40MHz
Rout,
LOCK,
RCLK
RCLK
0.4*t_RCP
-
0.4*t_RCP
ns
ns
10
ns
10
ns
12
ns
12
ns
1.75*t_R
CP⁺⁵
1.75*t
RCP⁺⁷
1.75*t
RCP⁺¹
0
ns
1.75*t_R 1.75*t 1.75*t
CP⁺⁶ RCP⁺⁷ RCP⁺⁹
ns
t_DSR1
Deserializer PLL LOCK Time
from PWRDN (with
SYNCPAT)
See Figure 4
See ⁽⁵⁾
40MHz
20MHz
3
us
10
us
(4) Because the Bus LVDS serial data stream is not decoded, the maximum frequency of the CHTST output driver could be exceeded if the
data stream were switched to CHTST. The maximum frequency of the BUS LVDS input should not exceed the parallel clock rate.
(5) For the purpose of specifying deserializer PLL performance t_DSR1 and t_DSR2 are specified with the REFCLK running and stable, and
specific conditions of the incoming data stream (SYNCPATs). t_DSR1 is the time required for the deserializer to indicate lock upon power-
up or when leaving the power-down mode. t_DSR2 is the time required to indicate lock for the powered-up and enabled deserializer when
the input (RI+ and RI−) conditions change from not receiving data to receiving synchronization patterns (SYNCPATs). The time to lock
to random data is dependent upon the incoming data.
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