DS92LV1260_14 Datasheet, PDF (8/21 Pages) Texas Instruments – Six Channel 10 Bit BLVDS Deserializer

DS92LV1260
SNLS134F – DECEMBER 2000 – REVISED APRIL 2013
www.ti.com
PWRDN
H
REN
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
X
H
L
SEL2
L
L
L
L
H
H
H
H
X
X
Control Pins Truth Table⁽¹⁾
SEL1
SEL0
Rout
L
L
Din6
Decoded to
Rout 0
(0:9) ⁽²⁾
L
H
Din6
Decoded to
Rout 1
(0:9) ⁽²⁾
H
L
Din6
Decoded to
Rout 2
(0:9) ⁽²⁾
H
H
Din6
Decoded to
Rout 3
(0:9) ⁽²⁾
L
L
Din6
Decoded to
Rout 4
(0:9) ⁽²⁾
L
H
Din6
Decoded to
Rout 5
(0:9) ⁽²⁾
H
L
Din6 is not
Decoded
H
H
Din6 is not
Decoded
X
X
Z
X
X
Z
CHTST
Din0 (not
decoded)
Din1 (not
decoded)
Din2 (not
decoded)
Din3 (not
decoded)
Din4 (not
decoded)
Din5 (not
decoded)
Z
Din6 (not
decoded)
Z
Z
LOCK[0:5]
Active ⁽³⁾
RCLK[0:5]
Active^{(4) (2)}
Active ⁽³⁾
Active^{(4) (2)}
Active ⁽³⁾
Active^{(4) (2)}
Active ⁽³⁾
Active^{(4) (2)}
Active ⁽³⁾
Active^{(4) (2)}
Active ⁽³⁾
Active^{(4) (2)}
Active ⁽³⁾
Active ⁽³⁾
Z
Active ⁽³⁾
Active^{(4) (2)}
Active^{(4) (2)}
Z
Z
(1) The routing of the Din inputs to the Deserializers and to the CHTST outputs are dependent on the states of SEL [0:2].
(2) Rout n[0:9] and RCLK [0:5] are Tri-Stated when LOCKn[0:5] is High.
(3) LOCK Active indicates that the LOCK output will reflect the state of it's respective Deserializer with regard to the selected data stream.
(4) RCLK Active indicates that the RCLK will be running if the Deserializer is locked. The timing of RCLK [0:5] with respect to Rout [0:5][0:9]
is determined by RCLK_R/F Figure 6
FUNCTIONAL DESCRIPTION
The DS92LV1260 combines six 1:10 deserializers into a single chip. Each of the six deserializers accepts a
BusLVDS data stream from Texas Instruments' DS92LV1021 or DS92LV1023 Serializer. The deserializers then
recover the clock and data to deliver the resulting 10-bit wide words to the outputs. A seventh serial data input
provides n+1 redundancy capability. The user can program the seventh input to be an alternative input to any of
the six deserializers. Whichever input is replaced by the seventh input is then routed to the CHANNEL TEST
(CHTST) pin on receiver output port.
Each of the 6 channels acts completely independent of each other. Each independent channel has outputs for a
10-bit wide data word, the recovered clock out, and the lock-detect output.
The DS92LV1260 has three operating states: Initialization, Data Transfer, and Resynchronization. In addition,
there are two passive states: Powerdown and TRI-STATE.
The following sections describe each operating mode and passive state.
Initialization
Before the DS92LV1260 receives and deserializes data, it and the transmitting serializer devices must initialize
the link. Initialization refers to synchronizing the Serializer's and the Deserializer's PLL's to local clocks. The local
clocks must be the same frequency or within a specified range if from different sources. After all devices
synchronize to local clocks, the Deserializers synchronize to the Serializers as the second and final initialization
step.
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