DS92LV1260_14 Datasheet, PDF (10/21 Pages) Texas Instruments – Six Channel 10 Bit BLVDS Deserializer

DS92LV1260
SNLS134F – DECEMBER 2000 – REVISED APRIL 2013
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USING THE DS92LV1021 AND DS92LV1260
The DS92LV1260 combines six 1:10 deserializers into a single chip. Each of the six deserializers accepts a
BusLVDS data stream up to 480 Mbps from Texas Instruments' DS92LV1021 or DS92LV1023 Serializer. The
deserializers then recover the embedded two clock bits and data to deliver the resulting 10-bit wide words to the
output. A seventh serial data input provides n+1 redundancy capability. The user can program the seventh input
to be an alternative input to any of the six deserializers. Whichever input is replaced by the seventh input is then
routed to the CHANNEL TEST (CHTST) pin on receiver output port. The Deserializer uses a separate reference
clock (REFCLK) and an onboard PLL to extract the clock information from the incoming data stream and then
deserialize the data. The Deserializer monitors the incoming clock information, determines lock status, and
asserts the LOCKn output high when loss of lock occurs.
POWER CONSIDERATIONS
An all CMOS design of the Deserializer makes it an inherently low power device.
POWERING UP THE DESERIALIZER
The DS92LV1260 can be powered up at any time by following the proper sequence. The REFCLK input can be
running before the Deserializer powers up, and it must be running in order for the Deserializer to lock to incoming
data. The Deserializer outputs will remain in TRI-STATE until the Deserializer detects data transmission at its
inputs and locks to the incoming data stream.
TRANSMITTING DATA
Once you power up the Deserializer, it must be phase locked to the transmitter to transmit data. Phase locking
occurs when the Deserializer locks to incoming data or when the Serializer sends sync patterns. The Serializer
sends SYNC patterns whenever the SYNC1 or SYNC2 inputs are high. The LOCKn output of the Deserializer
remains high until it has locked to the incoming data stream. Connecting the LOCKn output of the Deserializer to
one of the SYNC inputs of the Serializer will ensure that enough SYNC patterns are sent to achieve Deserializer
lock.
The Deserializer can also lock to incoming data by simply powering up the device and allowing the “random lock”
circuitry to find and lock to the data stream.
NOISE MARGIN
While the Deserializer LOCKn output is low, data at the Deserializer outputs (ROUT0-9) are valid, except for the
specific case of loss of lock during transmission which is further discussed in the RECOVERING FROM LOCK
LOSS section below.
The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still
reliably receive data. Various environmental and systematic factors include:
Serializer: TCLK jitter, V_CC noise (noise bandwidth and out-of-band noise)
Media: ISI, Large V_CM shifts
Deserializer: V_CC noise
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