DS92LV1260_14 Datasheet, PDF (1/21 Pages) Texas Instruments – Six Channel 10 Bit BLVDS Deserializer

DS92LV1260
www.ti.com
SNLS134F – DECEMBER 2000 – REVISED APRIL 2013
DS92LV1260 Six Channel 10 Bit BLVDS Deserializer
Check for Samples: DS92LV1260
FEATURES
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•2 Deserializes One to Six BusLVDS Input Serial
Data Streams with Embedded Clocks
• Seven Selectable Serial Inputs to Support n+1
Redundancy of Deserialized Streams
• Seventh Channel has Single Pin Monitor
Output That Reflects Input From Seventh
Channel Input
• Parallel Clock Rate up to 40MHz
• On Chip Filtering for PLL
• Absolute Maximum Worst Case Power
Dissipation = 1.9W at 3.6V
• High Impedance Inputs Upon Power Off (V_cc =
0V)
• Single Power Supply at +3.3V
• 196-pin NFBGA Package (Low-profile Ball Grid
Array) Package
• Industrial Temperature Range Operation:
−40°C to +85°C
DESCRIPTION
The DS92LV1260 integrates six deserializer devices
into a single chip. The chip uses a 0.25u CMOS
process technology. The DS92LV1260 can
simultaneously deserialize up to six data streams that
have been serialized by the Texas Instruments
DS92LV1021 or DS92LV1023 Bus LVDS serializers.
The device also includes a seventh serial input
channel that serves as a redundant input.
Each deserializer block in the DS92LV1260 operates
independently with its own clock recovery circuitry
and lock-detect signaling.
The DS92LV1260 uses a single +3.3V power supply
with a typical power dissipation of 1.2W at 3.3V with
a PRBS-15 pattern. Refer to the Connection
Diagrams for packaging information.
Block Diagram
Figure 1. Application
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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