DS92LV1260_14 Datasheet, PDF (12/21 Pages) Texas Instruments – Six Channel 10 Bit BLVDS Deserializer

DS92LV1260
SNLS134F – DECEMBER 2000 – REVISED APRIL 2013
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range 0.001 µF to 0.1 µF. Tantalum capacitors may be in the range 2.2 µF to 10 µF. Voltage rating for
tantalum capacitors should be at least 5X the power supply voltage being used. Randomly distributed by-
pass capacitors should also be used.
– Package and pin layout permitting, it is also recommended to use two vias at each power pin as well as all
RF bypass capacitor terminals. Dual vias reduce the interconnect inductance between layers by up to half,
thereby reducing interconnect inductance and extending the effective frequency range of the bypass
components.
– The outer layers of the PCB may be flooded with additional ground planes. These planes will improve
shielding and isolation as well as increase the intrinsic capacitance of the power supply plane system.
Naturally, to be effective, these planes must be tied to the ground supply plane at frequent intervals with
vias. Frequent via placement improves signal integrity on signal transmission lines by providing short
paths for image currents, which reduces signal distortion. Depending on which is greater, the planes
should be pulled back from all transmission lines and component mounting pads a distance equal to the
width of the widest transmission line or the thickness of the dielectric separating the transmission line from
the internal power or ground plane(s). Doing so minimizes effects on transmission line impedances and
reduces unwanted parasitic capacitances at component mounting pads.
• Use a termination resistor which best matches the differential impedance of your transmission line.
• Leave unused Bus LVDS receiver inputs open (floating).
– Limit traces on unused inputs to <0.5 inches.
• Isolate TTL signals from Bus LVDS signals.
• Use controlled impedance media.
– The backplane and connectors should have a matched differential impedance.
For a typical application circuit, please see Figure 9.
There are more common practices which should be followed when designing PCBs for LVDS signaling. General
application guidelines and hints may be found in the following application notes: AN-808 (SNLA028), AN-903
(SNLA034), AN-971 (SNLA165), AN-977 (SNLA166), and AN-1108 (SNLA008). For packaging information on
BGA's, please see AN-1126 (SNOA021).
USING T_DJIT AND T_RNM TO VALIDATE SIGNAL QUALITY
The parameter t_RNM is calculated by first measuring how much of the ideal bit the receiver needs to ensure
correct sampling. After determining this amount, what remains of the ideal bit that is available for external
sources of noise is called t_RNM.
The vertical limits of the mask are determined by the DS92LV1260 receiver input threshold of +/− 50mV.
Please refer to the eye mask pattern of Figure 11 for a graphic representation of t_DJIT and t_RNM.
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