DS92LV1260_14 Datasheet, PDF (4/21 Pages) Texas Instruments – Six Channel 10 Bit BLVDS Deserializer

DS92LV1260
SNLS134F – DECEMBER 2000 – REVISED APRIL 2013
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Electrical Characteristics⁽¹⁾ (continued)
Basic functionality and specifications per deserializer channel will be similar to DS92LV1212A. Over recommended operating
supply and termperature ranges unless otherwise specified.⁽²⁾
Parameter
Test Conditions
Pin/Freq.
Min Typ Max Units
t_DSR2
Deserializer PLL Lock Time
from SYNCPAT
See Figure 5
See ⁽⁵⁾
40MHz
20MHz
2
us
5
us
t_RNM
Deserializer Noise Margin
See ⁽⁶⁾
40MHz
20MHz
450 920
ps
1200 1960
ps
(6) t_RNM is a measure of how much phase noise (jitter)the deserializer can tolerate in the incoming data stream before bit errors occur. The
Deserializer Noise Margin is Specified By Design (GBD) using statistical analysis.
AC Timing Diagrams and Test Circuits
Figure 2. Deserializer Delay t_DD
Figure 3. Output Timing t_ROS and t_ROH
4
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