DS92LV1260_14 Datasheet, PDF (11/21 Pages) Texas Instruments – Six Channel 10 Bit BLVDS Deserializer

DS92LV1260
www.ti.com
SNLS134F – DECEMBER 2000 – REVISED APRIL 2013
RECOVERING FROM LOCK LOSS
In the case where the Deserializer loses lock during data transmission, up to 1 cycle of data that was previously
received can be invalid. This is due to the delay in the lock detection circuit. The lock detect circuit requires that
invalid clock information be received 2 times in a row to indicate loss of lock. Since clock information has been
lost, it is possible that data was also lost during these cycles. Therefore, after the Deserializer relocks to the
incoming data stream and the Deserializer LOCKn pin goes low, at least one previous data cycle should be
suspect for bit errors.
The Deserializer can relock to the incoming data stream by making the Serializer resend SYNC patterns, as
described above, or by random locking, which can take more time, depending on the data patterns being
received.
HOT INSERTION
All the BusLVDS devices are hot pluggable if you follow a few rules. When inserting, ensure the Ground pin(s)
makes contact first, then the VCC pin(s), and then the I/O pins. When removing, the I/O pins should be
unplugged first, then the VCC, then the Ground. Random lock hot insertion is illustrated in Figure 12.
TRANSMISSION MEDIA
The Serializer and Deserializer can also be used in point-to-point configurations, through PCB trace, or through
twisted pair cable. In point-to-point configurations, the transmission media need only be terminated at the
receiver end. Please note that in point-to-point configurations, the potential of offsetting the ground levels of the
Serializer vs. the Deserializer must be considered. Also, Bus LVDS provides a +/− 1V common mode range at
the receiver inputs.
FAILSAFE BIASING FOR THE DS92LV1260
The DS92LV1260 has internal failsafe biasing and an improved input threshold sensitivity of +/− 50mV versus
+/− 100mV for the DS92LV1210 or DS92LV1212. This allows for greater differential noise margin in the
DS92LV1260. However, in cases where the receiver input is not being actively driven, the increased sensitivity of
the DS92LV1260 can pickup noise as a signal and cause unintentional locking . For example, this can occur
when the input cable is disconnected.
External resistors can be added to the receiver circuit board to prevent noise pick-up. Typically, the non-inverting
receiver input is pulled up and the inverting receiver input is pulled down by high value resistors. The pull-up and
pull-down resistors (R₁ and R₂) provide a current path through the termination resistor (R_L) which biases the
receiver inputs when they are not connected to an active driver. The value of the pull-up and pull-down resistors
should be chosen so that enough current is drawn to provide a +15mV drop across the termination resistor.
Please see Figure 10 for the Failsafe Biasing Setup.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the DS92LV1260 should be designed to provide noise-free power to the
device. Good layout practice will separate high frequency or high level inputs and outputs to minimize unwanted
stray noise pickup, feedback and interference. There are a few common practices which should be followed
when designing PCB’s for Bus LVDS Signaling. Recommended layout practices are:
• Use at least 4 PCB board layers (Bus LVDS signals, ground, power, and TTL signals).
– Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for
power/ground sandwiches. This increases the intrinsic capacitance of the PCB power system which
improves power supply filtering, especially at high frequencies, and makes the value and placement of
external bypass capacitors less critical.
• Keep Serializers and Deserializers as close to the (Bus LVDS port side) connector as possible.
– Longer stubs lower the impedance of the bus, increase the load on the Serializer, and lower the threshold
margin at the Deserializers. Deserializer devices should be placed much less than one inch from slot
connectors. Because transition times are very fast on the Serializer Bus LVDS outputs, reducing stub
lengths as much as possible is the best method to ensure signal integrity.
• Bypass each Bus LVDS device and also use distributed bulk capacitance between power planes.
– Surface mount capacitors placed close to power and ground pins work best. External bypass capacitors
should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
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