DS90CR486_15 Datasheet, PDF (9/22 Pages) Texas Instruments – 133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)

DS90CR486
www.ti.com
SNLS149C – FEBRUARY 2003 – REVISED MARCH 2013
Table 1. DS90CR486 Outputs Mapped to DS90CR485 Outputs/DS90CR483 Inputs (continued)
DS90CR486 Receiver Output
DS90CR485 Transmitter Input *
RxOUT17
E2-D17
RxOUT18
E2-D18
RxOUT19
E2-D19
RxOUT20
E2-D20
RxOUT21
E2-D21
RxOUT22
E2-D22
RxOUT23
E2-D23
RxOUT24
E1-D0
RxOUT25
E1-D1
RxOUT26
E1-D2
RxOUT27
E1-D3
RxOUT28
E1-D4
RxOUT29
E1-D5
RxOUT30
E1-D6
RxOUT31
E1-D7
RxOUT32
E1-D8
RxOUT33
E1-D9
RxOUT34
E1-D10
RxOUT35
E1-D11
RxOUT36
E1-D12
RxOUT37
E1-D13
RxOUT38
E1-D14
RxOUT39
E1-D15
RxOUT40
E1-D16
RxOUT41
E1-D17
RxOUT42
E1-D18
RxOUT43
E1-D19
RxOUT44
E1-D20
RxOUT45
E1-D21
RxOUT46
E1-D22
RxOUT47
E1-D23
* E1 = Falling Edge and E2 = Rising Edge of RxCLK P/M Input Clock Edge
DS90CR483 Transmitter Input
TxIN17
TxIN18
TxIN19
TxIN20
TxIN21
TxIN22
TxIN23
TxIN24
TxIN25
TxIN26
TxIN27
TxIN28
TxIN29
TxIN30
TxIN31
TxIN32
TxIN33
TxIN34
TxIN35
TxIN36
TxIN37
TxIN38
TxIN39
TxIN40
TxIN41
TxIN42
TxIN43
TxIN44
TxIN45
TxIN46
TxIN47
DS90CR486 PIN DESCRIPTIONS — CHANNEL LINK RECEIVER⁽¹⁾
Pin Name
RxINP
RxINM
RxOUT
RxCLKP
RxCLKM
RxCLKOUT
PLLSEL
I/O
No.
Description
I
8
Positive LVDS differential data inputs.
I
8
Negative LVDS differential data inputs.
O
48
LVCMOS/LVTTL level data outputs. In PowerDown (PD = Low) mode, receiver
outputs are forced to a Low state.
I
1
Positive LVDS differential clock input.
I
1
Negative LVDS differential clock input.
O
1
LVCMOS/LVTTL level clock output. The rising edge acts as data strobe.
I
1
Control input for PLL range select. This pin must be tied to V_CC. No connect or
tied to GND is reserved for future use.
(1) These receivers have input fail-safe bias circuitry to ensure a stable receiver output for floating or terminated receiver inputs. Under
these conditions receiver inputs will be in a HIGH state. If a clock signal is present, outputs will all be HIGH; if the cable inter-connects
are disconnected which results in floating/terminated inputs, the outputs will remain in the last valid state. A floating/terminated clock
input will result in a LOW clock output.
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