DS90CR486_15 Datasheet, PDF (6/22 Pages) Texas Instruments – 133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)

DS90CR486
SNLS149C – FEBRUARY 2003 – REVISED MARCH 2013
www.ti.com
Figure 5. DS90CR486 Phase Lock Loop Set Time (V_CC > 3.0V)
Figure 6. DS90CR486 Power Down Delay
C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and
max
Tppos—Transmitter output pulse position (min and max)
RSKMD = ISI (Inter-symbol interference) + TPPOS(variance) + LVDS Source Clock Jitter (cycle to cycle)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
Refer to transmitter datasheet for Cycle-to-cycle LVDS Output jitter specification.
ISI is dependent on interconnect length; may be zero. Pre-emphasis in the transimitter is used to reduce the ISI.
Refer to transmitter datasheet for more information.
Figure 7. Receiver Skew Margin with DESKEW (RSKMD)
6
Submit Documentation Feedback
Product Folder Links: DS90CR486
Copyright © 2003–2013, Texas Instruments Incorporated