DS90CR486_15 Datasheet, PDF (11/22 Pages) Texas Instruments – 133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)

DS90CR486
www.ti.com
SNLS149C – FEBRUARY 2003 – REVISED MARCH 2013
APPLICATIONS INFORMATION
DC BALANCE
In addition to data information an additional bit is transmitted on every LVDS data signal line during each cycle
as shown in Figure 9. This bit is the DC balance bit (DCB). The purpose of the DC Balance bit is to minimize the
short- and long-term DC bias on the signal lines. This is achieved by selectively sending the data either
unmodified or inverted.
The value of the DC balance bit is calculated from the running word disparity and the data disparity of the current
word to be sent. The data disparity of the current word shall be calculated by subtracting the number of bits of
value 0 from the number of bits value 1 in the current word. Initially, the running word disparity may be any value
between +7 and −6. The running word disparity shall be calculated as a continuous sum of all the modified data
disparity values, where the unmodified data disparity value is the calculated data disparity minus 1 if the data is
sent unmodified and 1 plus the inverse of the calculated data disparity if the data is sent inverted. The value of
the running word disparity shall saturate at +7 and −6.
The value of the DC balance bit (DCB) shall be 0 when the data is sent unmodified and 1 when the data is sent
inverted. To determine whether to send data unmodified or inverted, the running word disparity and the current
data disparity are used. If the running word disparity is positive and the current data disparity is positive, the data
shall be sent inverted. If the running word disparity is positive and the current data disparity is zero or negative,
the data shall be sent unmodified. If the running word disparity is negative and the current data disparity is
positive, the data shall be sent unmodified. If the running word disparity is negative and the current data disparity
is zero or negative, the data shall be sent inverted. If the running word disparity is zero, the data shall be sent
inverted.
DC Balance mode is set when the BAL pin on the transmitter and receiver are tied HIGH - see DS90CR486 PIN
DESCRIPTIONS — CHANNEL LINK RECEIVER.
DESKEW
The "DESKEW” function on this receiver will deskew or compensate fixed interconnect skew between data
signals, with respect to the rising edge of the LVDS clock, on each of the independent differential pairs (pair-to-
pair skew). The deskew initialization or calibration is done automatically when the device is powered up. The
control pin CON1 must set High and the Deskew pin must set to High on the DS90CR486. However, the Deskew
calibration can also be performed after the device is powered up. De-asserting with a pulse of duration greater
than four clock cycles to the Deskew pin to restart the calibration of deskew. The calibration takes 4096 clock
cycles to complete after the TX and RX PLLs lock (20ms). No RxIN data is sampled during this period. The data
outputs during this period will be Low. For normal operation, deskew pin must set to High. Setting the deskew pin
to Low or No Connect will continuously re-calibrate the sampling strobes. Data outputs are Low during this
period.
In order for the deskew function to work properly, it must be intialized. The DS90CR486 deskew can be initialized
with any data pattern with a minimum of 1 transition per clock cycle; however, having multiple transition per clock
cycle will further improve the chance for the deskew circuit to find the optimal edge. Therefore, there are mulitiple
ways to initialize the deskew function depending on the setup configuration (Please refer to Figure 10). For
example, to initialize the operation of deskew using DS90CR485 and DS90CR486 in DC balance mode, the
DS_OPT pin at the input of the transmitter DS90CR485 can be set High OR Low when powered up. The period
of this input to the DS_OPT pin must be at least 20ms (TX and RX PLLs lock time) plus 4096 clock cycles in
order for the receiver to complete the deskew operation. For other configuration setup with DS90CR483 and
DS90CR484, please refer to the flow chart on Figure 10.
The DS_OPT pin at the input of the transmitter (DS90CR485) can be used to initiate the deskew calibration
pattern. Depends on the configuration, it can be set High or applied Low when power up in order for the receiver
to complete the deskew operation. For this reason, the LVDS clock signal with DS_OPT applied high (active data
sampling) shall be 1111000 or 1110000 pattern and the LVDS data lines (TxOUT 0-7) shall be High for one clock
cycle and Low for the next clock cycle. During the deskew operation with DS_OPT applied low, the LVDS clock
signal shall be 1111100 or 1100000 pattern. The transmitter will also output a series of 1111000 or 1110000 onto
the LVDS data lines (TxOUT 0-7) during deskew so that the receiver can automatically calibrated the data
sampling strobes at the receiver inputs. Each data channel is deskewed independently and is tuned over a
specific range. Please refer to corresponding receiver datasheet for a list of deskew ranges.
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR486
Submit Documentation Feedback
11