DS90CR486_15 Datasheet, PDF (5/22 Pages) Texas Instruments – 133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)

www.ti.com
AC Timing Diagrams
DS90CR486
SNLS149C – FEBRUARY 2003 – REVISED MARCH 2013
The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/LVTTL I/O.
Figure 1. “Worst Case” Test Pattern
Figure 2. DS90CR486 LVCMOS/LVTTL Output Load and Transition Times
Figure 3. DS90CR486 Setup/Hold and High/Low Times
Figure 4. DS90CR486 Propagation Delay - Latency
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: DS90CR486
Submit Documentation Feedback
5