DS90CR486_15 Datasheet, PDF (10/22 Pages) Texas Instruments – 133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)

DS90CR486
SNLS149C – FEBRUARY 2003 – REVISED MARCH 2013
Pin Name
PD
I/O
No.
I
1
DESKEW
I
1
BAL
I
1
CON1
V_CC
GND
PLLV_CC
PLLGND
LVDSV_CC
LVDSGND
NC
I
1
I
6
I
8
I
1
I
2
I
2
I
3
6
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Description
Power Down pin. This pin must be tied to input level of 2.5V to Vcc for normal
operation. When de-asserted (low input) the receiver outputs are Low. Please refer
to the APPLICATIONS INFORMATION on the back for more information.
This pin must be tied to logic High or Vcc for normal operation of Deskew function.
De-asserting a pulse of duration greater than 4 clock cycles will restart the deskew
initialization. Do NOT tie this pin to LOW. Please refer to the APPLICATIONS
INFORMATION on the back for more information.
LVCMOS/LVTTL level input. This pin must be tied to logic High or Vcc to enable
DC Balance function(Figure 9). When tied low or left open, the DC Balance function
is disabled(Figure 8). Please refer to the APPLICATIONS INFORMATION on the
back for more infomation.
Control Pin. This pin must be tied to logic High or Vcc.
Power supply pins for LVCMOS/LVTTL outputs and digital circuitry.
Ground pins for LVCMOS/LVTTL outputs and digital circuitry.
Power supply for PLL circuitry.
Ground pin for PLL circuitry.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
No Connect. Make NO Connection to these pins - leave open.
10
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