DS90CR486_15 Datasheet, PDF (4/22 Pages) Texas Instruments – 133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)

DS90CR486
SNLS149C – FEBRUARY 2003 – REVISED MARCH 2013
Receiver Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
RSRC
RxOUT Data valid before RxCLK OUT,
f = 133 MHz
2.0
3.5
(Figure 3)
f = 100 MHz
3.0
4.7
f = 66 MHz
5.0
7.0
RHRC
RxOUT Data valid after RxCLK OUT, (Figure 3) f = 133 MHz
2.5
4.1
f = 100 MHz
3.5
5.0
f = 66 MHz
6.0
8.0
RPDL
Receiver Propagation Delay - Latency, (Figure 4)
2(TCIP)+5
2(TCIP)+10
RPLLS Receiver Phase Lock Loop Set ,(Figure 5)
RPDD
Receiver Powerdown Delay, (Figure 6)
RSKMD Receiver Skew Margin with Deskew, BAL=Low f = 133 MHz
275
(Figure 7), ⁽²⁾
f = 100 MHz
400
f = 66 MHz
500
RDR
Receiver Deskew Range
f = 133 MHz
−150
f = 100 MHz
−200
f = 66 MHz
−200
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Max
2(TCIP)+15
10
1
+150
+200
+200
Units
ns
ns
ns
ns
ns
ns
ns
ms
µs
ps
ps
ps
ps
ps
ps
(2) Receiver Skew Margin with Deskew (RSKMD) is defined as the valid data sampling region at the receiver inputs. The DESKEW function
will constrain the receiver’s sampling strobes to the middle half of the LVDS bit and removes (adjusts for) fixed interconnect skew. This
margin (RSKMD) allows for inter-symbol interference (dependent on type/length of cable), Transmitter Pulse Position (TPPOS) variance,
and LVDS clock jitter (TJCC).RSKMD ≥ ISI + TPPOS(variance) + LVDS Source Clock Jitter (cycle to cycle). See APPLICATIONS
INFORMATION section for more details.
4
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