DS90CR486_15 Datasheet, PDF (1/22 Pages) Texas Instruments – 133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)

DS90CR486
www.ti.com
SNLS149C – FEBRUARY 2003 – REVISED MARCH 2013
DS90CR486 133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)
Check for Samples: DS90CR486
FEATURES
1
•2 Up to 6.384 Gbps Throughput
• 66MHz to 133MHz Input Clock Support
• Reduces Cable and Connector Size and Cost
• Cable Deskew Function
• DC Balance Reduces ISI Distortion
• For Point-to-Point Backplane or Cable
Applications
• Low Power, 890 mW Typ at 133MHz
• Flow through Pinout for Easy PCB Design
• +3.3V Supply Voltage
• 100-pin TQFP Package
• Conforms to TIA/EIA-644-A-2001 LVDS
Standard
DESCRIPTION
The DS90CR486 receiver converts eight Low Voltage
Differential Signaling (LVDS) data streams back into
48 bits of LVCMOS/LVTTL data. Using a 133MHz
clock, the data throughput is 6.384Gbit/s
(798Mbytes/s).
The multiplexing of data lines provides a substantial
cable reduction. Long distance parallel single-ended
buses typically require a ground wire per active signal
(and have very limited noise rejection capability).
Thus, for a 48-bit wide data and one clock, up to 98
conductors are required. With this Channel Link
chipset as few as 19 conductors (8 data pairs, 1 clock
pair and a minimum of one ground) are needed. This
provides an 80% reduction in interconnect width,
which provides a system cost savings, reduces
connector physical size and cost, and reduces
shielding requirements due to the cables' smaller
form factor.
The DS90CR486 deserializer is improved over prior
generations of Channel Link devices and offers
higher bandwidth support and longer cable drive with
three areas of enhancement. To increase bandwidth,
the maximum clock rate is increased to 133 MHz and
8 serialized LVDS outputs are provided. Cable drive
is enhanced with a user selectable pre-emphasis (on
DS90CR485) feature that provides additional output
current during transitions to counteract cable loading
effects. Optional DC balancing on a cycle-to-cycle
basis, is also provided to reduce ISI (Inter-Symbol
Interference). With pre-emphasis and DC balancing,
a low distortion eye-pattern is provided at the receiver
end of the cable. A cable deskew capability has been
added to deskew long cables of pair-to-pair skew.
These three enhancements allow long cables to be
driven.
The DS90CR486 is intended to be used with the
DS90CR485 Channel Link Serializer. It is also
backward compatible with serializers DS90CR481
and DS90CR483. The DS90CR486 is footprint
compatible with the DS90CR484.
The chipset is an ideal solution to solve EMI and
interconnect size problems for high-throughput point-
to-point applications.
For more details, please refer to the APPLICATIONS
INFORMATION section of this datasheet.
1
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2
PRODUCTION DATA information is current as of publication date.
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Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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