DS90CR486_15 Datasheet, PDF (12/22 Pages) Texas Instruments – 133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)

DS90CR486
SNLS149C – FEBRUARY 2003 – REVISED MARCH 2013
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Note that the deskew initialization must be performed at least once after the PLL has locked to the input clock
frequency, and it must be done at the time when the receiver is powered up and PLL has locked. If power is lost,
or if the cable has been swithcd or disconnected, the initialization procedure must be repeated or else the
receiver may not sample the incoming LVDS data correctly.
POWER DOWN
The receiver provides a power down feature. When de-asserted current draw through the supply pins is
minimized and the PLLs are shut down. The receiver outputs are forced to an active LOW state when in the
power down mode. (See DS90CR486 Pin Descriptions — Channel Link Receiver Table). This is not a
LVCMOS/LVTTL input pin and has a high input threshold. For normal operation, this pin must be tied to an input
level of 2.5V to Vcc.
CONFIGURATIONS
The chipset is designed to be connected typically to a single receiver load. This is known as a point-to-point
configuration. It is also possible to drive multiple receiver loads if certain restrictions are made(i.e. low data rate).
Only the final receiver at the end of the interconnect should provide termination across the pair. In this case, the
driver still sees the intended DC load of 100 Ohms. Receivers connected to the cable between the transmitter
and the final receiver must not load down the signal. To meet this system requirement, stub lengths from the line
to the receiver inputs must be kept very short.
CABLE TERMINATION
A termination resistor is required for proper operation to be obtained. The termination resistor should be equal to
the differential impedance of the media being driven. This should be in the range of 90 to 132 Ohms. 100 Ohms
is a typical value common used with standard 100 Ohm twisted pair cables. This resistor is required for control of
reflections and also to complete the current loop. It should be placed as close to the receiver inputs to minimize
the stub length from the resistor to the receiver input pins.
HOW TO CONFIGURE FOR BACKPLANE APPLICATIONS
In a backplane application with differential line impedance of 100Ω the differential line pair-to-pair skew can
controlled by trace layout. The transmitter-DS90CR485 “DS_OPT” pin may be set high. In a backplane
application with short PCB distance traces, pre-emphasis from the transmitter is typically not required. The “PRE”
pin should be left open (do not tie to ground). A resistor pad provision for a pull up resistor to Vcc can be
implemented in case pre-emphasis is needed to counteract heavy capacitive loading effects.
SUPPLY BYPASS RECOMMENDATIONS
Bypass capacitors must be used on the power supply pins. Different pins supply different portions of the circuit,
therefore capacitors should be nearby all power supply pins except as noted in the DS90CR486 Pin
Descriptions — Channel Link Receiver table. Use high frequency ceramic (surface mount recommended) 0.1μF
capacitors close to each supply pin. If space allows, a 0.01μF capacitor should be used in parallel, with the
smallest value closest to the device pin. Additional scattered capacitors over the printed circuit board will improve
decoupling. Multiple (large) via should be used to connect the decoupling capacitors to the power plane. A 4.7 to
10μF bulk cap is recommended near the PLLVCC pins and also the LVDSVCC pins. Connections between the
caps and the pin should use wide traces.
RECEIVER OUTPUT DRIVE STRENGTH
The DS90CR486 output specifies a 8pF load, V_OH and V_OL are tested at ± 2mA, which is intended for only 1 or
maybe 2 loads. The DS90CR486 receiver’s output driving capability has improved over prior generation of
Channel Link devices. Additional buffering at the receiver output is not necessary. If high fan-out is required or
long transmission line driving capability, buffering the receiver output is recommended. Receiver outputs do not
support / provide a TRI-STATE function.
LVDS INTERCONNECT GUIDELINES
See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details.
• Use 100Ω coupled differential pairs
• Use the S/2S/3S rule in spacings
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