DS64MB201_13 Datasheet, PDF (9/32 Pages) Texas Instruments – Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis

DS64MB201
www.ti.com
SNLS307E – JANUARY 2011 – REVISED JULY 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified.⁽¹⁾
Symbol
Parameter
Conditions
Min
Typ
Max
DJ4
Residual Deterministic Jitter at 3.2 Tx Launch Amplitude = 0.8 to
Gbps
1.2 Vp–p, 20” 4–mil FR4 trace,
EQx = off, DEMx = −6 dB,
VOD = 1.0 Vp-p, K28.5, RATE = 0
See ⁽⁸⁾
0.07 0.18
Units
UI_P-P
Electrical Characteristics — Serial Management Bus Interface
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
SERIAL BUS INTERFACE DC SPECIFICATIONS
V_IL
Data, Clock Input Low Voltage
V_IH
Data, Clock Input High Voltage
2.1
I_PULLUP
Current Through Pull-Up Resistor High Power Specification
or Current Source
4
V_DD
I_LEAK-Bus
I_LEAK-Pin
C_I
R_TERM
Nominal Bus Voltage
Input Leakage Per Bus Segment
Input Leakage Per Device Pin
Capacitance for SDA and SDC
External Termination Resistance
pull to V_DD = 2.5V ± 5% OR 3.3V ±
10%
See ⁽¹⁾
See ⁽¹⁾ and ⁽²⁾
V_DD3.3,
See ⁽¹⁾, ⁽²⁾, and ⁽³⁾
V_DD2.5,
(1)_, (2)_{, and} (3)
2.375
-200
SERIAL BUS INTERFACE TIMING SPECIFICATIONS. See Figure 6
FSMB
Bus Operating Frequency
See ⁽⁴⁾
10
TBUF
Bus Free Time Between Stop and
Start Condition
4.7
THD:STA
Hold time after (Repeated) Start
At I_PULLUP, Max
Condition. After this period, the first
4.0
clock is generated.
TSU:STA
Repeated Start Condition Setup
Time
4.7
TSU:STO
Stop Condition Setup Time
4.0
THD:DAT
Data Hold Time
300
TSU:DAT
Data Setup Time
250
T_TIMEOUT
Detect Clock Low Timeout
See ⁽⁴⁾
25
T_LOW
Clock Low Period
4.7
T_HIGH
Clock High Period
See ⁽⁴⁾
4.0
T_LOW:SEXT
Cumulative Clock Low Extend Time See ⁽⁴⁾
(Slave Device)
t_F
Clock/Data Fall Time
See ⁽⁴⁾
t_R
Clock/Data Rise Time
See ⁽⁴⁾
t_POR
Time in which a device must be
See ⁽⁴⁾
operational after power-on reset
Typ
-15
2000
1000
Max
0.8
3.6
3.6
+200
10
100
35
50
2
300
1000
500
Units
V
V
mA
V
µA
µA
pF
Ω
Ω
kHz
µs
µs
µs
µs
ns
ns
ms
µs
µs
ms
ns
ns
ms
(1) Recommended value. Parameter not tested in production.
(2) Recommended maximum capacitance load per bus segment is 400pF.
(3) Maximum termination voltage should be identical to the device supply voltage.
(4) Compliant to SMBus 2.0 physical layer specification. See System Management Bus (SMBus) Specification Version 2.0, section 3.1.1
SMBus common AC specifications for details.
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