DS64MB201_13 Datasheet, PDF (14/32 Pages) Texas Instruments – Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis

DS64MB201
SNLS307E – JANUARY 2011 – REVISED JULY 2013
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System Management Bus (SMBus) and Configuration Registers
The System Management Bus interface is compatible to SMBus 2.0 physical layer specification. ENSMB must be
pulled high to enable SMBus mode and allow access to the configuration registers.
The DS64MB201 has the AD[3:0] inputs in SMBus mode. These pins set the SMBus slave address inputs. The
AD[3:0] pins have internal pull-down. When left floating or pulled low the AD[3:0] = 0000'b, the device default
address byte is A0'h. Based on the SMBus 2.0 specification, the DS64MB201 has a 7-bit slave address of
1010000'b. The LSB is set to 0'b (for a WRITE), thus the 8-bit value is 1010 0000'b or A0'h. The bold bits
indicate the AD[3:0] pin map to the slave address bits [4:1]. The device address byte can be set with the use of
the AD[3:0] inputs. Below are some examples.
AD[3:0] = 0001'b, the device address byte is A2'h
AD[3:0] = 0010'b, the device address byte is A4'h
AD[3:0] = 0100'b, the device address byte is A8'h
AD[3:0] = 1000'b, the device address byte is B0'h
The SDC and SDA pins are 3.3V LVCMOS signaling and include high-Z internal pull up resistors. External low
impedance pull up resistors maybe required depending upon SMBus loading and speed. Note, these pins are not
5V tolerant.
Transfer of Data via the SMBus
During normal operation the data on SDA must be stable during the time when SDC is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SDC is High indicates a message START condition.
STOP: A Low-to-High transition on SDA while SDC is High indicates a message STOP condition.
IDLE: If SDC and SDA are both High for a time exceeding t_BUF from the last detected STOP condition or if they
are High for a total exceeding the maximum specification for t_HIGH then the bus will transfer to the IDLE state.
SMBus Transactions
The device supports WRITE and READ transactions. See Table 8 for register address, type (Read/Write, Read
Only), default value and function information.
When SMBus is enabled, all outputs of the DS64MB201 must use one of the following De-emphasis settings
(Table 7). The driver de-emphasis value is set on a per lane basis using 6 different registers. Each register
(0x18, 0x26, 0x2E, 0x35, 0x3C, 0x43) requires one of the following De-emphasis settings when in SMBus mode.
The VOD for each output should be set via register write or pin control to be a minimum of 1000 mV.
Table 7. De-Emphasis Register Settings (must write one of the following when in SMBus mode)
De-Emphasis Value
0.0 dB
-3.5 dB
-6 dB
-9 dB
-12 dB
Register Setting
0x01
0xE8
0x88
0x90
0xA0
3 Gbps Operation
10” trace or 1 meter 28 awg cable
20” trace or 2 meters 28 awg cable
25” trace or 3 meters cable
5 meters 28 awg cable
8 meters 28 awg cable
6 Gbps Operation
5” trace or 0.5 meter 28 awg cable
10” trace or 1meters 28 awg cable
20” trace or 2 meters cable
3 meters 28 awg cable
5 meters 28 awg cable
Writing a Register
To write a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
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