DS64MB201_13 Datasheet, PDF (3/32 Pages) Texas Instruments – Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis

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Pin Diagram
DS64MB201
SNLS307E – JANUARY 2011 – REVISED JULY 2013
SMBUS AND CONTROL
NC 1
NC 2
DOUT0+ 3
DOUT0- 4
NC 5
NC 6
DOUT1+ 7
DOUT1- 8
VDD 9
DIN0+ ¹⁰
DIN0- ¹¹
NC 12
NC 13
VDD 14
DIN1+ 15
DIN1- 16
NC ¹⁷
NC 18
TOP VIEW
DAP = GND
45 SIA0+
44 ^SIA0-
43 SIB0+
42 SIB0-
41 VDD
40 SIA1+
39 SIA1-
38 _SIB1+
37 SIB1-
36 VDD
35 SOA0+
34 SOA0-
33 SOB0+
32 SOB0-
31 SOA1+
30 ^SOA1-
29 SOB1+
28 SOB1-
The center DAP on the package bottom is the device GND connection. This pad must be connected to GND through
multiple (minimum of 4) vias to ensure optimal electrical and thermal performance.
Figure 2. DS64MB201 Pin Diagram 54L WQFN
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Product Folder Links: DS64MB201
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