DS64MB201_13 Datasheet, PDF (5/32 Pages) Texas Instruments – Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis

DS64MB201
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Pin Name
TXIDLEDO
TXIDLESO
FANOUT
SEL0, SEL1
VOD0, VOD1
Analog
SD_TH
Power
VDD
GND
NC
Pin Number
24
25
26
19, 20
22, 23
SNLS307E – JANUARY 2011 – REVISED JULY 2013
Table 1. Pin Descriptions (continued)
I/O, Type⁽¹⁾ Pin Description
I, Float,
LVCMOS
TXIDLEDO, 3–level input controls the driver output.
TXIDLEDO = 0 disables the signal detect/squelch function for DOUT.
TXIDLEDO = 1 forces the DOUT to be muted (electrical idle).
TXIDLEDO = Float enables the signal auto detect/squelch function for DOUT and
the signal detect voltage threshold level can be adjusted using the SD_TH pin. See
Table 4
I, Float,
LVCMOS
TXIDLESO, 3–level input controls the driver output.
TXIDLESO = 0 disables the signal detect/squelch function for SOUT.
TXIDLESO = 1 forces the SOUT to be muted (electrical idle).
TXIDLESO = Float enables the signal auto detect/squelch function for SOUT and
the signal detect voltage threshold level can be adjusted using the SD_TH pin. See
Table 4
I, LVCMOS w/ FANOUT = 1 enables both A/B outputs for broadcast mode.
internal pull- FANOUT = 0 disables one of the outputs depending on the SEL0, SEL1 pin. See
down
Table 6
I, LVCMOS w/ SEL0 is for lane 0, SEL1 is for lane 1
internal pull- SEL0, SEL1 = 0 selects B input and B output.
down
SEL0, SEL1 = 1 selects A input and A output. See Table 6
I, LVCMOS w/
internal pull-
down
VOD[1:0] adjusts the output differential amplitude voltage level on all outputs.
00 set output VOD = 600 mVp-p (Default)
01 sets output VOD = 800 mVp-p
10 sets output VOD = 1000 mVp-p
11 sets output VOD = 1200 mVp-p
Note: VOD should be set to a minimum of 1000 mV to achieve stated DE levels.
27
I, ANALOG Threshold select pin for electrical idle detect threshold. Float pin for default 130
mVp-p (differential).
See Table 5
9, 14, 36, 41,
51
DAP, 52
Power
Power
1, 2, 5, 6, 12,
13, 17, 18
2.5V Power supply pins.
DAP is the large metal contact at the bottom side, located at the center of the 54
pin WQFN package. It should be connected to the GND plane with at least 4 via to
lower the ground impedance and improve the thermal performance of the package.
NOTE: DAP is the primary GND
No Connect — Leave pin open
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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