DS64MB201_13 Datasheet, PDF (10/32 Pages) Texas Instruments – Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis

DS64MB201
SNLS307E – JANUARY 2011 – REVISED JULY 2013
Timing Diagrams
Figure 3. LPDS Output Transition Times
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Figure 4. Propagation Delay Timing Diagram
Figure 5. Idle Timing Diagram
t_LOW
t_R
t_HIGH
t_BUF
t_HD:STA
t_HD:DAT
t_F
t_SU:STA
t_SU:DAT
SP
ST
ST
Figure 6. SMBus Timing Parameters
t_SU:STO
SP
SCL
SDA
10
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