DS64MB201_13 Datasheet, PDF (1/32 Pages) Texas Instruments – Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis

DS64MB201
www.ti.com
SNLS307E – JANUARY 2011 – REVISED JULY 2013
DS64MB201 Dual Lane 2:1/1:2 Mux/Buffer with Equalization and
De-Emphasis
Check for Samples: DS64MB201
FEATURES
1
•2 Up to 6.4 Gbps dual lane 2:1 mux, 1:2 switch
or fan-out
• Adjustable receive equalization up to +33 dB
gain
• Adjustable transmit de-emphasis up to −12 dB
• Adjustable transmit VOD
• <0.25 UI of residual DJ at 6.4 Gbps with 40”
FR4 trace
• SATA/SAS: OOB signal pass-through
• Adjustable electrical IDLE detect threshold
• Low power
• Signal conditioning programmable via pin
selection or SMBus interface
• Single 2.5V supply operation
• >6 kV HBM ESD Rating
• 3.3V tolerant SMBus interface
• High speed signal flow–thru pinout package:
54-pin WQFN (10 mm x 5.5 mm)
APPLICATIONS
• SAS and SATA (1.5, 3.0 and 6 Gbps)
• XAUI (3.125 Gbps), RXAUI (6.25 Gbps)
• sRIO – Serial Rapid I/O
• Fibre Channel (4.25 Gbps)
• 10GBase-CX4, InfiniBand (SDR & DDR)
• FR-4 backplane traces
DESCRIPTION
The DS64MB201 is a dual lane 2:1 multiplexer and
1:2 switch or fan-out buffer with signal conditioning
suitable for SATA/SAS and other high-speed bus
applications up to 6.4 Gbps. The device performs
both receive equalization and transmit de-emphasis,
allowing maximum flexibility of physical placement
within a system. The receiver's continuous time linear
equalizer (CTLE) provides a boost of up to +33 dB at
3 GHz and is capable of opening an input eye that is
completely closed due to inter-symbol interference
(ISI) induced by the interconnect medium. The
transmitter features a programmable output de-
emphasis driver and allows amplitude voltage levels
to be selected from 600 mVp-p to 1200 mVp-p to suit
multiple application scenarios. The signal conditioning
settings are programmable via control pin settings or
SMBus interface.
To enable seamless upgrade from SAS/SATA 3.0
Gbps to 6.0 Gbps data rates without compromising
physical reach, DS64MB201 automatically detects
the incoming data rate and selects the optimal de-
emphasis pulse width. The device detects the out-of-
band (OOB) idle and active signals of the SAS/SATA
specification and passes through with minimum signal
distortion.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated