DS64MB201_13 Datasheet, PDF (15/32 Pages) Texas Instruments – Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis

DS64MB201
www.ti.com
SNLS307E – JANUARY 2011 – REVISED JULY 2013
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may
now occur.
Reading a Register
To read a register, the following protocol is used (see SMBus 2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and communication with other SMBus devices may now
occur.
Recommended SMBus Register Settings
When SMBus mode is enabled (ENSMB = 1), the default register settings are not configured to an appropriate
level. Below is the recommended settings to configure the EQ, VOD and DE to a medium level that supports
interconnect length of 20 inches FR4 trace or 3 to 5 meters of cable length. Please refer to Table 2, Table 3,
Table 7, Table 8 for additional information and recommended settings.
1. Reset the SMBus registers to default values:
– Write 01'h to 0x00.
2. Set de-emphasis to -6 dB for all lanes:
– Write 88'h to 0x18, 0x26, 0x2E, 0x35, 0x3C, 0x43.
3. Set equalization to external pin level EQ[1:0] = 00 (~9 dB at 3 GHz) for all lanes:
– Write 30'h to 0x0F, 0x16, 0x1D, 0x24, 0x2C, 0x3A.
4. Set VOD = 1.0 Vp-p for all lanes:
– Write 0F'h to 0x17, 0x25, 0x2D, 0x34, 0x3B, 0x42.
Address Register Name
0x00
Reset
0x01
PWDN lanes
Table 8. SMBus Register Map
Bit (s) Field
7:1 Reserved
0
Reset
7:0 PWDN CHx
Type Default
R/W 0x00
R/W 0x00
Description
Set bits to 0.
SMBus Reset
1: Reset registers to default value
Power Down per lane
[7]: NC — SOB1
[6]: DIN1 — SOA1
[5]: NC — SOB0
[4]: DIN0 — SOA0
[3]: SIB1 — DOUT1
[2]: SIA1 — NC
[1]: SIB0 — DOUT0
[0]: SIA0 — NC
00'h = all lanes enabled
FF'h = all lanes disabled
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