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DS64MB201_13 Datasheet, PDF (16/32 Pages) Texas Instruments – Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis
DS64MB201
SNLS307E – JANUARY 2011 – REVISED JULY 2013
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0x02
0x03
0x08
0x0F
0x12
0x15
PWDN Control
SEL / FANOUT
Control
Pin Control Override
SIA0
EQ Control
SIA0
IDLE Threshold
DOUT0
IDLE RATE Select
Table 8. SMBus Register Map (continued)
7:1 Reserved
R/W 0x00
0
PWDN Control
7:3 Reserved
2
SEL1
R/W 0x00
1
SEL0
0
FANOUT
7:5 Reserved
R/W 0x00
4
Override IDLE
3
Reserved
2
Override RATE
1
Override SEL
0
Override
FANOUT
7:6 Reserved
5:0 SIA0 EQ
R/W 0x20
7:4 Reserved
R/W 0x00
3:0 IDLE threshold
7:6 Reserved
5
IDLE auto
4
IDLE select
3:2 Reserved
1
RATE auto
0
RATE select
R/W 0x00
Set bits to 0.
0: Normal operation
1: Enable PWDN control in Register 0x01
Set bits to 0.
0: Selects SIB1 input and SOB1 output
1: Selects SIA1 input and SOA1 output
0: Selects SIB0 input and SOB0 output
1: Selects SIA0 input and SOA0 output
0: Enable only A or B output depends on SEL1 and
SEL0 (SeeTable 6)
1: Enable both SOAn and SOBn output
Set bits to 0.
0: Allow IDLE pin control
1: Block IDLE pin control
Set bit to 0.
0: Allow RATE pin control
1: Block RATE pin control
0: Allow SEL pin control
1: Block SEL pin control
0: Allow FANOUT pin control
1: Block FANOUT pin control
Set bits to 0.
SIA0 EQ Control - total of 24 levels
(3 gain stages with 8 settings)
[5]: Enable EQ
[4:3]: Gain Stage Control
[2:0]: Boost Level Control
Register [EN] [GST] [BST] = Hex Value
100000 = 20'h = Bypass (Default)
101010 = 2A'h = 5 dB at 3 GHz
110000 = 30'h = 9 dB at 3 GHz
110010 = 32'h = 11.7 dB at 3 GHz
111001 = 39'h = 14.6 dB at 3 GHz
110101 = 35'h = 18.4 dB at 3 GHz
110111 = 37'h = 20 dB at 3 GHz
111011 = 3B'h = 21.2 dB at 3 GHz
111101 = 3D'h = 28.4 dB at 3 GHz
Set bits to 0.
De-assert = [3:2], assert = [1:0]
00 = 110 mV, 70 mV (Default)
01 = 150 mV, 110 mV
10 = 170 mV, 130 mV
11 = 190 mV, 150 mV
Set bits to 0.
0: Allow IDLE_sel control in Bit 4
1: Automatic IDLE detect
0: Output is ON (SD is disabled)
1: Output is muted (electrical idle)
Set bits to 0.
0: Allow RATE_sel control in Bit 0
1: Automatic RATE detect
0: 2.5 to 3.2 Gbps
1: 5.0 to 6.4 Gbps
16
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