DS64MB201_13 Datasheet, PDF (4/32 Pages) Texas Instruments – Dual Lane 2:1/1:2 Mux/Buffer with Equalization and De-Emphasis

DS64MB201
SNLS307E – JANUARY 2011 – REVISED JULY 2013
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Table 1. Pin Descriptions
Pin Name
Pin Number I/O, Type⁽¹⁾ Pin Description
Differential High Speed I/O's
SIA0+, SIA0-,
SIA1+, SIA1-
45, 44,
40, 39
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated on-chip
50Ω termination resistor connects SIA_n+ to VDD and SIA_n- to VDD when
enabled.
SOA0+, SOA0-,
35, 34,
O
SOA1+, SOA1-
31, 30
Inverting and non-inverting low power differential signaling 50Ω outputs with de-
emphasis. Fully compatible with AC coupled CML inputs.
SIB0+, SIB0-,
SIB1+, SIB1-
43, 42,
38, 37
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated on-chip
50Ω termination resistor connects SIB_n+ to VDD and SIB_n- to VDD when
enabled.
SOB0+, SOB0-,
33, 32,
O
SOB1+, SOB1-
29, 28
Inverting and non-inverting low power differential signaling 50Ω outputs with de-
emphasis. Fully compatible with AC coupled CML inputs.
DIN0+, DIN0-,
DIN1+, DIN1-
10, 11,
15, 16
I, CML
Inverting and non-inverting CML differential inputs to the equalizer. A gated on-chip
50Ω termination resistor connects SIB_n+ to VDD and SIB_n- to VDD when
enabled.
DOUT0+, DOUT0-, 3, 4,
O
DOUT1+, DOUT1- 7, 8
Inverting and non-inverting low power differential signaling 50Ω outputs with de-
emphasis. Fully compatible with AC coupled CML inputs.
Control Pins — Shared (LVCMOS)
ENSMB
48
I, LVCMOS w/ System Management Bus (SMBus) enable pin.
internal pull- HIGH = Register Access: Provides access to internal digital registers to control
down
such functions as equalization, de-emphasis, VOD, rate, channel powerdown, and
idle detection threshold.
LOW = Pin Mode: Access to the SMBus registers are disabled and control pins are
used to program VOD, rate, idle detection, equalization and de-emphasis settings.
Please refer to System Management Bus (SMBus) and Configuration Registers
section and Electrical Characteristics — Serial Management Bus Interface for
detailed information.
ENSMB = 1 (SMBUS MODE)
SDA, SCL
49, 50
I, LVCMOS
ENSMB = 1
The SMBus SDA (data input/output bi-directional) and SCL (clock input) pins are
enabled.
AD[3:0]
54, 53, 47, 46 I, LVCMOS w/ ENSMB = 1
internal pull- SMBus Slave Address Inputs. In SMBus mode, these pins are the user set SMBus
down
slave address inputs.
ENSMB = 0 (NORMAL PIN MODE)
EQA,
EQB,
EQD
46,
I, Float,
EQA/B/D, 3–level input controls the level of equalization.
49,
LVCMOS
EQA controls the level of equalization of the SIA0 and SIA1 inputs.
53
EQB controls the level of equalization of the SIB0 and SIB1 inputs.
EQD controls the level of equalization of the DIN0 and DIN1 inputs.
The pins are active only when ENSMB is de-asserted (Low).
When ENSMB goes high the SMBus control registers provide independent control
of each lane. See Table 2
DEMA,
DEMB,
DEMD
47,
I, Float,
DEMA/B/D, 3–level input controls the level of de-emphasis.
50,
LVCMOS
DEMA controls the level of de-emphasis of the SOA0 and SOA1 outputs.
54
DEMB controls the level of de-emphasis of the SOB0 and SOB1 outputs.
DEMD controls the level of de-emphasis of the DOUT0 and DOUT1 outputs.
The pins are active only when ENSMB is de-asserted (Low).
When ENSMB goes High the SMBus control registers provide independent control
of each lane. See Table 3
Control Pins — Both Modes (LVCMOS)
RATE
21
I, Float,
RATE, 3–level input controls the pulse width of de-emphasis of the output.
LVCMOS
RATE = 0 forces ~3 Gbps,
RATE = 1 forces ~6 Gbps,
RATE = Float enables auto rate detection. See Table 3
(1) 1 = HIGH, 0 = LOW, FLOAT = 3rd input state. FLOAT condition; Do not drive pin; pin is internally biased to mid level with 50 kΩ pull-
up/pull-down. Internal pulled-down = Internal 30 kΩ pull-down resistor to GND is present on the input. Input edge rate for
LVCMOS/FLOAT inputs must be faster than 50 ns from 10–90%.
4
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