TM4C1299KCZAD Datasheet, PDF (859/2014 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1299KCZAD Microcontroller
11.4.3.4
Speed of Transactions
The COUNT0 field in the EPIBAUD register must be configured to set the main transaction rate
based on what the slave device can support (including wiring considerations). The main control
transitions are normally ½ the baud rate (COUNT0 = 1) because the EPI block forces data versus
control to change on alternating clocks. When using dual chip selects, each chip select can access
the bus using differing baud rates by setting the CSBAUD bit in the EPIHBnCFG2 register. In this
case, the COUNT0 field controls the CS0n transactions, and the COUNT1 field controls the CS1n
transactions. When using quad chip select mode, the COUNT0 bit field of the EPIBAUD2 register
controls the baud rate of CS2n and the COUNT1 bit field is programmed to control the baud rate of
CS3n.
Additionally, the Host-Bus mode provides read and write wait states for the data portion to support
different classes of device. These wait states stretch the data period (hold the rising edge of data
strobe) and may be used in all four sub-modes. The wait states are set using the WRWS and RDWS
bits in the EPI Host-Bus n Configuration (EPIHBnCFGn) register. The WRWS and RDWS bits are
enhanced with more precision by WRWSM and RDWSM bits in the EPIHBnTIMEn registers. Note none
of the wait state configuration bits can be set concurrently with the BURST bit in the same
EPIHBnCFGn register. See Table 11-11 on page 859 for programming information.
Table 11-11. Data Phase Wait State Programming
RDWS or WRWS Encoding in
EPIHBnCFGn Register
0x0
0x0
0x1
0x1
0x2
0x2
0x3
0x3
RDWSM or WRWSM Encoding in
EPIHBnTIMEn Registers
Data Phase Wait States
1
1 EPI clocks
0
2 EPI clocks
1
3 EPI clocks
0
4 EPI clocks
1
5 EPI clocks
0
6 EPI clocks
1
7 EPI clocks
0
8 EPI clocks
The CAPWIDTH bit in EPIHBnTIMEn registers controls the delay between Host-Bus transfers. When
the CSBAUD bit is set and multi-chip selects have been configured in the EPIHBnCFG2 registers,
delay takes an additional clock cycle to adjust the clock rate of different chip selects.
Word read and write transactions can be enhanced through the enabling of the BURST bit in the
EPIHB16CFGn registers.
11.4.3.5
Sub-Modes of Host Bus 8/16
The EPI controller supports four variants of the Host-Bus model using 8 or 16 bits of data in all four
cases. The four sub-modes are selected using the MODE bits in the EPIHBnCFG register, and are:
1. Address and data are muxed. This scheme is used by many 8051 devices, some Microchip PIC
parts, and some ATmega parts. When used for standard SRAMs, a latch must be used between
the microcontroller and the SRAM. This sub-mode is provided for compatibility with existing
devices that support data transfers without a latch (that is, CPLDs). In general, the de-muxed
sub-mode should normally be used. The ALE configuration should be used in this mode, as all
Host-Bus accesses have an address phase followed by a data phase. The ALE indicates to an
external latch to capture the address then hold until the data phase. The ALE configuration is
controlled by configuring the CSCFG and CSCFGEXT field to be 0x0 in the EPIHBnCFG2 register.
June 18, 2014
859
Texas Instruments-Production Data