TM4C1299KCZAD Datasheet, PDF (1564/2014 Pages) Texas Instruments – Tiva Microcontroller

Ethernet Controller
Register 46: Ethernet MAC Target Time Nanoseconds (EMACTARGNANO),
offset 0x720
The MAC Target Time Seconds (EMACTARGSEC) register, along with the MAC Target Time
Nanoseconds (EMACTARGNANO) register, is used to schedule an interrupt event.
Ethernet MAC Target Time Nanoseconds (EMACTARGNANO)
Base 0x400E.C000
Offset 0x720
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TRGTBUSY
TTSLO
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TTSLO
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31
Name
TRGTBUSY
Type
RW
Reset
0x0
Description
Target Time Register Busy
This bit is set and cleared by the MAC.
Value Description
0 The Ethernet MAC Target Time Seconds/Nanoseconds
(EMACTARGSEC/EMACTARGNANO) registers are not busy.
1 The Ethernet MAC Target Time Seconds/Nanoseconds
(EMACTARGSEC/EMACTARGNANO) registers are busy. This
bit is set when the PPSCTRL field in the EMACPPSCTRL register
is programmed to 0x2 or 0x3 and the MAC is instructed to
synchronize the EMACTARGSEC/EMACTARGNANO registers
to the PTP clock domain.
Note:
The EMACTARGSEC and EMACTARGNANO
registers must not be updated when this bit is read
as 1.
30:0
TTSLO
RW
0x0
Target Timestamp Low Register
This register stores the time in (signed) nanoseconds. When the value
of the timestamp matches both EMACTARGx registers, the MAC starts
or stops the PPS signal output and generates an interrupt (if enabled)
based on the TRGMODS0 field in the MAC PPS Control
(EMACPPSCTRL) register.
This value should not exceed 0x3B9A.C9FF when DGTLBIN is set in
the EMACTIMSTCTRL register. The actual start or stop time of the PPS
signal output may have an error margin up to one unit of sub-second
increment value.
1564
Texas Instruments-Production Data
June 18, 2014