TM4C1299KCZAD Datasheet, PDF (1078/2014 Pages) Texas Instruments – Tiva Microcontroller

Analog-to-Digital Converter (ADC)
Figure 15-4. Doubling the ADC Sample Rate
ADC Sample Clock
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GSYNC
ADC 0 PHASE 0x0 (0.0°)
ADC 1 PHASE 0x8 (180.0°)
Using the ADCSPC register, ADC0 and ADC1 may provide a number of interesting applications:
■ Coincident continuous sampling of different signals. The sample sequence steps run coincidently
in both converters. In this situation, the TSHn of matching sample steps of both ADC module
sequencers must be the same and the PHASE field must be 0x0 in both ADC module ADCSPC
registers. The TSHn field is found in the ADC Sample Sequence n Sample and Hold Time
(ADCSSTSHn) register.
– ADC Module 0, ADCSPC = 0x0, sampling AIN0
– ADC Module 1, ADCSPC = 0x0, sampling AIN1
Note: If two ADCs are configured to sample the same signal, a skew (phase lag) must be
added to one of the ADC modules to prevent coincident sampling. Phase lag can be
added by programming the PHASE field in the ADCSPC register.
■ Skewed sampling of the same signal. The skew is determined by both the TSHn field in the
ADCSSTSHn registers and the PHASE field in the ADCSPC register. For the fastest skewed
sample rate, all TSHn fields must be programmed to 0x0. If TSHn=0x0 for all sequencers and
the PHASE field of one ADC is 0x8, the configuration doubles the conversion bandwidth of a
single input when software combines the results as shown in Figure 15-5 on page 1079.
– ADC Module 0, ADCSPC = 0x0, sampling AIN0
– ADC Module 1, ADCSPC = 0x8, sampling AIN0
Note that it is not required that the TSHn fields be the same in a skewed sample. If an application
has varying analog input resistance, then TSHn and PHASE may vary according to operational
requirements.
1078
Texas Instruments-Production Data
June 18, 2014