TM4C1299KCZAD Datasheet, PDF (323/2014 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1299KCZAD Microcontroller
Register 40: CAN 1 Power Domain Status (CAN1PDS), offset 0x2A0
This register provides the status of power to the CAN 1 SRAM memory array.
Note:
The CAN1 memory array does not support retention and can only be turned ON and OFF.
If the memory array is currently turned on (PWRCTL = 0x3) and the power control to CAN1
is subsequently removed by clearing the P1 bit of the PCCAN register, the event causes
the memory array to turn off and the MEMSTAT bit in the CAN1PDS register to be 0x0 (array
OFF).
CAN 1 Power Domain Status (CAN1PDS)
Base 0x400F.E000
Offset 0x2A0
Type RO, reset 0x0000.003F
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
reserved
MEMSTAT
PWRSTAT
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Bit/Field
31:6
5:4
3:2
Name
reserved
reserved
MEMSTAT
Type
RO
RO
RO
Reset
0
0x3
0x3
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Memory Array Power Status
Displays status of CAN1 SRAM memory
Value Description
0x0 Array OFF
0x1-0x2 Reserved
0x3 Array On
1:0
PWRSTAT
RO
0x3
Power Domain Status
Value Description
0x0 OFF
0x1-0x2 Reserved
0x3 ON
June 18, 2014
323
Texas Instruments-Production Data