TM4C1299KCZAD Datasheet, PDF (322/2014 Pages) Texas Instruments – Tiva Microcontroller

System Control
Register 39: CAN 0 Memory Power Control (CAN0MPC), offset 0x29C
This register provides power control to the peripheral memory array.
Note:
The CAN0 memory array does not support retention and can only be turned ON and OFF.
If the memory array is currently turned ON (PWRCTL = 0x3) and the power control to the
CAN0 is subsequently removed by clearing the P0 bit of the PCCAN register, the event
causes the memory array to turn off and the MEMSTAT bit in the CAN0PDS register to be
0x0 (array OFF).
CAN 0 Memory Power Control (CAN0MPC)
Base 0x400F.E000
Offset 0x29C
Type RW, reset 0x0000.0003
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
PWRCTL
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Bit/Field
31:2
1:0
Name
reserved
PWRCTL
Type
RO
RW
Reset
0
0x3
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Memory Array Power Control
Allows multiple levels of power control in peripheral's SRAM memory
space
Value Description
0x0 Array OFF
0x1-0x2 Reserved
0x3 Array On
322
June 18, 2014
Texas Instruments-Production Data