GC6016 Datasheet, PDF (7/46 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

GC6016
www.ti.com
SLWS227A – NOVEMBER 2010 – REVISED MARCH 2011
RECOMMENDED OPERATING CONDITIONS
V_DD
V_DDA
V_DDS
V_DDSHV
T_C
T_J
Core supply voltage
Analog supply for PLLs
Digital supply voltage for LVDS I/O
Digital supply voltage CMOS I/O
Case temperature
Junction temperature
310 MHz, 5.7 A max. ^(1)(2)(3)
60 mA max. (each)⁽¹⁾
700 mA max.⁽¹⁾
PC board design dependent
See ⁽⁴⁾
MIN TYP MAX UNIT
1.05 1.1 1.15 V
1.71 1.8 1.89 V
1.71 1.8 1.89 V
3.15 3.3 3.45 V
–40
30 90 °C
105 °C
(1) Chip specifications are production tested to 90°C case temperature. QA tests are performed at 85°C.
(2) Production tested hot using checksum at 310 MHz and maximum supplies. Power scales linearly with frequency with a dc consumption
around 350 mA typical, 700 mA worst case.
(3) Power consumption is a strong function of the configuration. A calculator is available to estimate power for a specific configuration.
(4) Reliability calculations presume junction temperature 105°C or below. Operation above 105°C junction temperature reduces product
lifetime.
THERMAL INFORMATION
GC6016
THERMAL METRIC
ZEV
UNIT
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
Junction-to-ambient thermal resistance⁽¹⁾
Junction-to-case (top) thermal resistance⁽²⁾
Junction-to-board thermal resistance⁽³⁾
Junction-to-top characterization parameter⁽⁴⁾
Junction-to-board characterization parameter⁽⁵⁾
Junction-to-case (bottom) thermal resistance⁽⁶⁾
484 PINS
15.4
2.1
7.6
0.5
7.5
N/A
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(4) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(5) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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