|
GC6016 Datasheet, PDF (37/46 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors | |||
|
◁ |
www.ti.com
DPD Clock
GC6016
SLWS227A â NOVEMBER 2010 â REVISED MARCH 2011
SYNCA, SYNCB
tsu
th
4 cycles, min.
Figure 21. SYNCA, SYNCB Timing to DPD Clock
T0514-01
Table 23. DPD Clock and Sync Out Switching Characteristics
td(SYNCOut)
tHO(SYNCOut)
PARAMETER
Data valid after DPD clock
Data held valid after next DPD clock
TEST CONDITIONS
See (1)
See (1)
MIN NOM MAX UNIT
0.95 ns
0.3
ns
(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested
at â40°C.
Sync Out
DPD Clock
td
tHO
T0515-01
Figure 22. Sync Out Timing to DPD Clock
The JTAG test connections are used with the CMOS signals for board interconnection tests. The TRSTB pin
must be toggled low, or low initially. If JTAG is not used, the TRSTB signal should be GROUNDed or tied to
GND through < 1 kΩ resistance. TRSTB should be 0 for normal operation.
Table 24. JTAG Switching Characteristics
fTCK
tTCKL
tTCKH
tsu(TDI,TMS)
tH(TDI,TMS)
td
tOHD(TDO)
PARAMETER
JTAG clock frequency
JTAG clock low period
JTAG clock high period
Input data setup time before fTCKâ
Input data hold time after fTCKâ
Output data delay from fTCKâ
Previous data valid from fTCKâ
TEST CONDITIONS
See (1)
See (1)
See (1)
See (1)
See (1)
See (1)
MIN MAX UNIT
50 MHz
10
ns
10
ns
7 ns
1.5
10 ns
2 ns
(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested
at â40°C.
Copyright © 2010â2011, Texas Instruments Incorporated
Product Folder Link(s): GC6016
Submit Documentation Feedback
37
|
▷ |