GC6016 Datasheet, PDF (40/46 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

GC6016
SLWS227A – NOVEMBER 2010 – REVISED MARCH 2011
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CEB
Addr
OEB
WEB
Data
t_su(WR)
t_su(WR)
t_su(WR)
t_low(WR)
t_h(WR)
t_h(WR)
t_high(WR)
t_h(WR)
Figure 26. MPU WRITE Timing Specifications
T0518-01
Power Sequencing Guideline
TI ASIC I/O design allows either the core supply (VDD) or the I/O supply (VDDS) to be powered up⁽²⁾ for an
indefinite period of time while the other power supply is not powered up, if all of these constraints are met:
• Chip is within all maximum ratings and recommended operating conditions.
• Have followed all warnings about exposure to maximum rated and recommended conditions, particularly
junction temperature. These apply to power transitions as well as normal operation.
• Bus contention while VDDS is powered up must be limited to 100 hours over the projected lifetime of the
device.
• Bus contention while VDDS is powered down may violate the absolute maximum ratings.
However, it is generally good practice to power up VDD, VDDSHV, and VDDS all within 1 second of each other.
Application Information
The GC5330/GC6016 evaluation module includes the following additional transmit/receive signal chain
components:
• TMS320C6748 digital signal processor (DSP)
• DAC3283 16-bit 800-MSPS, dac348X, or DAC5682 16-bit, 1-GSPS DAC (transmit path)
• CDCE72010 clock generator
• TRF3720 300-MHz to 4.8-GHz quadrature modulator with integrated wideband PLL/VCO
• TRF370317 0.4-GHz to 4-GHz quadrature modulator
• ADS41B49 14-bit, 250-MSPS ADC (and other options; feedback path)
• AMC7823 analog monitoring and control circuit with GPIO and SPI
• PGA870 wideband programmable gain amplifier
• ADS42b49 14-bit dual 250-MSPS receive or complex feedback ADC (and other options; RX path)
(2) A supply bus is powered up when the voltage is within the recommended operating range. It is powered down when it is below that
range, either stable or in transition.
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