GC6016 Datasheet, PDF (35/46 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

GC6016
www.ti.com
SLWS227A – NOVEMBER 2010 – REVISED MARCH 2011
Table 19. RX ADC-W14 Switching Characteristics
f_CLK(ADC)
t_su(ADC,A)
t_h(ADC,A)
t_su(ADC,B)
t_h(ADC,B)
PARAMETER
RX input clock frequency ADCA14 Clk,
ADCB14 Clk
Input data setup time on port A before
ADCA14 Clk transition
Input data hold time on port A after
ADCA14 Clk transition
Input data setup time on port B before
ADCB14 Clk transition
Input data hold time on port B after
ADCB14 Clk transition
TEST CONDITIONS
See ⁽¹⁾
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
MIN NOM MAX UNIT
620 MHz
160
ps
200
ps
180
ps
220
ps
(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested
at –40°C.
(2) Setup and hold times apply to data and appropriate ADC Clk, respectively. Timing is measured from ADC Clk threshold crossing.
Table 20. RX ADC-B7, B14 Switching Characteristics
f_CLK(ADC-AB)
f_CLK(ADC-C)
t_su(ADC,A)
t_h(ADC,A)
t_su(ADC,B)
t_h(ADC,B)
t_su(ADC,C)
t_h(ADC,C)
t_su(ADC,A)
t_h(ADC,A)
t_su(ADC,B)
t_h(ADC,B)
PARAMETER
RX input clock frequency, ADCA7 Clk,
ADCB7 Clk
RX input clock frequency, ADCC7 Clk
Input data setup time on port A before
ADCA7 Clk transition
Input data hold time on port A after
ADCA7 Clk transition
Input data setup time on port B before
ADCB7 Clk transition
Input data hold time on port B after
ADCB7 Clk transition
Input data setup time on port C before
ADCC7 Clk transition
Input data hold time on port C after
ADCC7 Clk transition
Input data setup time on port A before
ADCA14 Clk transition
Input data hold time on port A after
ADCA14 Clk transition
Input data setup time on port B before
ADCB14 Clk transition
Input data hold time on port B after
ADCB14 Clk transition
TEST CONDITIONS
See ⁽¹⁾
See ⁽¹⁾
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
See ^{(1) (2)}
MIN NOM MAX UNIT
620 MHz
620 MHz
260
ps
160
ps
170
ps
140
ps
290
ps
150
ps
130
ps
200
ps
170
ps
240
ps
(1) Chip specifications are production tested at 90°C case temperature for the given specification. Early production lots are sample tested
at –40°C.
(2) Setup and hold times apply to data and appropriate ADC Clk, respectively. Timing is measured from ADC Clk threshold crossing.
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