GC6016 Datasheet, PDF (33/46 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

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DAC Data, DAC Frame
GC6016
SLWS227A – NOVEMBER 2010 – REVISED MARCH 2011
DAC Data Clock
Min
Skew
Max
Skew
Min
Max
Skew
Skew
Ideal
Ideal
Data
Data
Placement
Placement
T0511-01
Figure 18. TX LVDS Timing Specifications (TXA and TXB) (DACCLK Aligned With Data)
The ADC output interface has two types of timing, based on the clock centered over the data, or clock
edge-aligned with the data. The GC6016 only processes clock centered over the data. Each ADC type is
characterized by the data and clock alignment, in Table 17, from which the proper table and timing diagram can
be determined as follows: ADC W7 in Table 18 and Figure 19; ADC W14 in Table 19 and Figure 20; and ADC
B7 in Table 20 and Figure 19. Note: The general ADC routing is to align the clock and data traces with a
common routing delay. For the ADS5463 and ADS5474 the clock trace must be adjusted in length to meet the
system timing design.
Note: when RXA is used as a baseband interface, the specification is shown in table Table 17. The table shows
a sampling of ADCs released at publication time. If the clock is not centered, the pc board may require added
routing delay to the clock out to satisfy the setup time requirements. See (*) in Table 17.
W7 – word-wide ADC interface, clock on bit 7
W14 – word-wide ADC interface, clock on bit 14
B7 – byte-wide ADC interface, clock on bit 7
B14 – byte-wide ADC interface, clock on bit 14
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