GC6016 Datasheet, PDF (5/46 Pages) Texas Instruments – Wideband Transmit-Receive Digital Signal Processors

GC6016
www.ti.com
SLWS227A – NOVEMBER 2010 – REVISED MARCH 2011
There are four DDUC blocks. Each can be used for the RX DDC downconversion or TX DUC upconversion, one
at a time. The DDUC has a complex mixer, cascade integrator comb filter, resampler, and a programmable FIR
filter. Each DDUC can support 1 to 12 channels.
The TX path can be configured for one, two, or four antenna streams. In addition, with one or two antenna
streams, an envelope modulator output is available. The DAC and envelope modulator share the same output
ports. The TX input is from the baseband input, through the DDUC to create complex antenna streams. The CFR
block provides for gain adjustment, peak reduction, and peak limiting. Additional interpolation stages after CFR
expand the antenna stream bandwidth.
Specialized capture logic collects the RX input, feedback input, RX output, CFR output, and DPD output for the
DSP processor to support built-in test. The capture logic can also be used for performance monitoring and power
measurement.
PART NUMBER
GC6016IZEV
T_C
–40°C to 85°C
AVAILABLE OPTIONS
PACKAGE
484 ball 23-mm × 23-mm PBGA
THERMAL PROPERTIES
Heat transfer through package top
GC6016
24 LVDS (1.8V) ^Baseband
Interface
24 LVDS (1.8V)
Power
Meter,
per
Channel
beAGC
(RX
Only)
per
Channel
TX
Complex
Gain per
Channel
1–12 Channel DDUC Block
(config as TX or RX, showing TX)
FIR
1´,
2´
Farrow
1–1024´
CIC
1–3´
Capture Buffer A
Capture Buffer B
Interval Based Power Meter
Running Avg Power Meter
Control and Sync CMOS (3.3 V)
NCO
X
TX
1–2 Streams
ET
Mux
and
Sum
CFR
UC
1/2´
TX
Eq
(TX)
or
Dist
2´
(RX)
Includes
interp ^{40% BW,}
before or ^{90 dB stop}
after CFR,
80% BW,
90 dB stop
X
BUC
IF NCO
1/2/3/4´
80% BW,
90 dB stop;
90% BW,
80 dB stop
TX
IF
Mux
and
Sum
RX 1/2/4 Streams
I/Q
Imbal
Correction
Eq
(16
Taps)
BDC
1/2/4/8/16´
IF
NCO
When I/Q correction
enabled, IF NCO is disabled
JTAG CMOS (3.3 V)
Switch
R2C
fe-
AGC
DC
Offset
Cancel
High-
Speed
Sync,
Clocks
16
8
4
2
2
uP data uP addr uP ctrl INT TESTMOD, SPI en, SPIDIO SPIDO
RESET SPI clk
(SPARE)
4
JTAG
NOTE: UC1 and UC2 are for CFR interpolation; UC2 can only be used if UC1 is also used.
40 LVDS (1.8V)
TX
Format
and
DAC
Interface
40 LVDS (1.8V)
1–4 TX Streams
Up to 8 DACs
(2 40-Pin Ports)
DVGA
Format/
GPIO
16 CMOS (3.3V)
ADC
inter-
face
(port
AB)
60 LVDS (1.8V)
Up to 8 ADCs
(2 30-Pin Ports)
ADC
inter-
face
(port C)
DPD clk
Sync A, B in
Sync out
16 LVDS (1.8V)
1 ADC
(1 16-Pin Port)
2 LVDS
4 LVDS
2 LVDS
LVDS
showing
the number
of pins;
each signal
is a diff. pair
B0445-02
Figure 5. GC6016 Block Diagram
GC6016 Introduction
The GC6016 is a flexible transmit and receive digital signal processor that includes receiver and transmitter
blocks, digital downconverter / upconverter (DDUC) blocks, crest factor reduction (CFR) engine, flexible LVDS
data converter and baseband interfaces, and capture buffers for adaptive filtering algorithms.
Each of the four DDUC blocks can be configured as either a digital downconverter (DDC) or a digital upconverter
(DUC). Typically, a system can be implemented as both TX and RX, with both DDC and DUC functions. The
DDUC blocks provide programmable FIR filters with flexible numbers of taps, depending on signal bandwidth and
number of channels, as well as fractional resamplers, CIC filters, and complex mixers. The DDUC complex
mixers support static or hopping tuning functions.
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): GC6016
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