DS92LV1021_14 Datasheet, PDF (7/23 Pages) Texas Instruments – 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer

DS92LV1021, DS92LV1210
www.ti.com
SNLS024C – MARCH 1999 – REVISED APRIL 2013
Deserializer Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ ⁽¹⁾
t_DSR1
Deserializer PLL Lock See ⁽²⁾
16MHz
7
Time from PWRDWN
(with SYNCPAT)
See Figure 14
See Figure 15
40MHz
4.8
t_DSR2
Deserializer PLL Lock
time from SYNCPAT
16MHz
7
40MHz
4.5
t_ZHLK
TRI-STATE to HIGH
Delay (power-up)
LOCK
1.5
t_RNM
Deserializer Noise
Margin
See Figure 16
See ⁽³⁾
16 MHz
400
40 MHz
100
1100
400
Max
Units
15
μs
25.6
μs
10
μs
7
μs
12
ns
ps
ps
(2) For the purpose of specifying deserializer PLL performance tDSR1 and tDSR2 are specified with the REFCLK running and stable, and
specific conditions of the incoming data stream (SYNCPATs). It is recommended that the derserializer be initialized using either tDSR1
timing or tDSR2 timing. tDSR1 is the time required for the deserializer to indicate lock upon power-up or when leaving the power-down
mode. Synchronization patterns should be sent to the device before initiating either condition. tDSR2 is the time required to indicate lock
for the powered-up and enabled deserializer when the input (RI+ and RI-) conditions change from not receiving data to receiving
synchronization patterns (SYNCPATs).
(3) tRNM is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur.
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