DS92LV1021_14 Datasheet, PDF (16/23 Pages) Texas Instruments – 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer

DS92LV1021, DS92LV1210
SNLS024C – MARCH 1999 – REVISED APRIL 2013
www.ti.com
Pin Name
PWRDN
LOCK
RCLK
REN
DVCC
DGND
AVCC
AGND
REFCLK
DESERIALIZER PIN DESCRIPTION (continued)
I/O
No.
Description
I
7
Powerdown. TTL level input. PWRDN driven low shuts down the PLL
and TRI-STATEs outputs putting the device into a low power sleep
mode.
O
10
LOCK goes low when the Deserializer PLL locks onto the embedded
clock edge. CMOS level output. Totem pole output structure, does not
directly support wire OR connection.
O
9
Recovered Clock. Parallel data rate clock recovered from embedded
clock. Used to strobe ROUT, CMOS level output.
I
8
Output Enable. TTL level input. TRI-STATEs ROUT0–ROUT9, LOCK
and RCLK when driven low.
I
21, 23
Digital Circuit power supply.
I
14, 20, 22
Digital Circuit ground.
I
4, 11
Analog power supply (PLL and Analog Circuits).
I
1, 12, 13
Analog ground (PLL and Analog Circuits).
I
3
Use this pin to supply a REFCLK signal for the internal PLL frequency.
Truth Table
DIN (0–9)
X
X
X
TCLK_R/F
X
X
X
DATA
1
DATA
0
RI
RI−
X
X
X
X
SYNC PTRN
DATA (0–9)
DATA (0–9)
SYNC
PTRN ⁽²⁾
DATA (0–9)⁽²⁾
DATA (0–9)⁽²⁾
TCLK
X
X
SYSTEM
CLK
RCLK_R/F
X
X
X
1
0
(1) Pulse 5-bits
(2) Inverted
(3) Device must be locked first
(4) Must be 1 before SYNC PTRN starts
SYNC1/SYNC2
X
X
1 ⁽¹⁾
0
0
REFCLK
X
X
SYSTEM CLK
SYSTEM CLK
SYSTEM CLK
DEN
X
0
1
1
1
REN
X
0 ⁽³⁾
1
1
1
PWRDN
0
1
1
1
1
PWRDN
0
1
1
1
1
DO+
DO−
Z
Z
Z
Z
SYNC PTRN
SYNC
PTRN ⁽²⁾
DATA (0–9) DATA (0–9)v
DATA (0–9) DATA (0–9)⁽²⁾
RCLK
LOCK
ROUT (0–9)
Z
Z
Z
Z
CLK
Z
Z
1 ⁽⁴⁾
SYNC PTRN
0
DATA
0
DATA
16
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