DS92LV1021_14 Datasheet, PDF (12/23 Pages) Texas Instruments – 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer

DS92LV1021, DS92LV1210
SNLS024C – MARCH 1999 – REVISED APRIL 2013
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Figure 15. Deserializer PLL Lock Time from SyncPAT
SW - Setup and Hold Time (Internal data sampling window)
t_JIT- Serializer Output Bit Position Jitter
t_RSM = Receiver Sampling Margin Time
Figure 16. Receiver Bus LVDS Input Skew Margin
V_OD = (DO⁺)–(DO^−).
Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode.
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