DS92LV1021_14 Datasheet, PDF (3/23 Pages) Texas Instruments – 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer

DS92LV1021, DS92LV1210
www.ti.com
SNLS024C – MARCH 1999 – REVISED APRIL 2013
Data Transfer
After initialization, the Serializer inputs DIN0–DIN9 may be used to input data to the Serializer. Data is clocked
into the Serializer by the TCLK input. The edge of TCLK used to strobe in data is selectable via the TCLK_R/F
pin. TCLK_R/F high selects the rising edge for clocking data and low selects the falling edge. If either of the
SYNC inputs is high for 5*TCLK cycles the data at DIN 0-DIN9 is ignored regardless of the clock edge.
A start bit and a stop bit, appended internally, frame the data bits in the register. The start bit is always high and
the stop bit is always low. The start and stop bits function as the embedded clock bits in the serial stream.
Serialized data and clock bits (10+2 bits) are transmitted from the serial data output (DO) at 12 times the TCLK
frequency. For example, if TCLK is 40 MHz, the serial rate is 40 × 12 = 480 Mega bits per second. Since only 10
bits are from input data, the serial “payload” rate is 10 times the TCLK frequency. For instance, if TCLK = 40
MHz, the payload data rate is 40 × 10 = 400 Mbps. TCLK is provided by the data source and must be in the
range 16 MHz to 40 MHz nominal.
The outputs (DO±) can drive a heavily loaded backplane or a point-to-point connection. The outputs transmit
data when the enable pin (DEN) is high, PWRDN = high and SYNC1 and SYNC2 are low. The DEN pin may be
used to TRI-STATE the outputs when driven low.
The LOCK pin on the Deserializer is driven low when it is synchronized with the Serializer. The Deserializer locks
to the embedded clock and uses it to recover the serialized data. ROUT data is valid when LOCK is low.
Otherwise ROUT0–ROUT9 is invalid.
RCLK pin is the reference to data on the ROUT0-ROUT9 pins. The polarity of the RCLK edge is controlled by
the RCLK_R/F input.
ROUT(0-9), LOCK and RCLK outputs will drive a minimum of three CMOS input gates (15 pF load) with 40 MHz
clock.
Resynchronization
The Deserializer LOCK pin driven low indicates that the Deserializer PLL is locked to the embedded clock edge.
If the Deserializer loses lock, the LOCK output will go high and the outputs (including RCLK) will be TRI-STATE.
The LOCK pin must be monitored by the system to detect a loss of synchronization and the system must arrange
to pulse the Serializer SYNC1 or SYNC2 pin to resynchronize. There are multiple approaches possible. One
recommendation is to provide a feedback loop using the LOCK pin itself to control the sync request of the
Serializer (SYNC1 or SYNC2). Otherwise, LOCK pin needs to be monitored and when it is a high, the system
needs to ensure that one or both of the Serializer SYNC inputs area asserted for at least 1024 cycles of TCLK. A
minimum of 1024 sync patterns are needed to resynchronize. Dual SYNC pins are provided for multiple control in
a multi-drop application.
Powerdown
The Powerdown state is a low power sleep mode that the Serializer and Deserializer may use to reduce power
when there is no data to be transferred. Powerdown is entered when PWRDN and REN are driven low on the
Deserializer, and when the PWRDN is driven low on the Serializer. In Powerdown, the PLL is stopped and the
outputs go into TRI-STATE, disabling load current and also reducing supply current to the milliamp range. To exit
Powerdown, PWRDN is driven high.
Both the Serializer and Deserializer must reinitialize and resynchronize before data can be transferred.
Initialization of the Serializer takes 1024 TCLK cycles. The Deserializer will initialize and assert LOCK high until it
is locked to the Bus LVDS clock.
TRI-STATE
For the Serializer, TRI-STATE is entered when the DEN pin is driven low. This will TRI-STATE both driver output
pins (DO+ and DO−). When DEN is driven high the serializer will return to the previous state as long as all other
control pins remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F).
For the Deserializer, TRI-STATE is entered when the REN pin is driven low. This will TRI-STATE the receiver
output pins (ROUT0–ROUT9), LOCK and RCLK.
Copyright © 1999–2013, Texas Instruments Incorporated
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