DS92LV1021_14 Datasheet, PDF (2/23 Pages) Texas Instruments – 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer

DS92LV1021, DS92LV1210
SNLS024C – MARCH 1999 – REVISED APRIL 2013
www.ti.com
Figure 1. Application
Functional Description
The DS92LV1021 and DS92LV1210 is a 10-bit Serializer / Deserializer chipset designed to transmit data over a
heavily loaded differential backplanes at clock speeds from 16 to 40MHz. It may also be used to drive data over
Unshielded Twisted Pair (UTP) cable.
The chipset has three active states of operation: Initialization, Data Transfer, and Resynchronization; and two
passive states: Powerdown and TRI-STATE.
The following sections describe each operation and passive state.
Initialization
Before data can be transferred both devices must be initialized. Initialization refers to synchronization of the
Serializer and the Deserializer PLL's to local clocks that may be the same or separate. Afterward,
synchronization of Deserializer to Serializer occurs as the second step of initialization.
Step 1: When V_CC is applied to both Serializer and/or Deserializer, the respective outputs are held in TRI-STATE
and internal circuitry is disabled by on-chip power-on circuitry. When V_CC reaches V_CC OK (2.5V) the PLL in each
device begins locking to a local clock. For the Serializer, the local clock is the transmit clock, TCLK, provided by
the source ASIC or other device. For the Deserializer, the local clock is provided by an on-board oscillator or
other source and applied to the REFCLK pin. After V_CC OK is reached the device's PLL will lock.
The Serializer outputs are held in TRI-STATE while the PLL locks to the TCLK. The Serializer is now ready to
send data or SYNC patterns depending on the levels of the SYNC1 and SYNC2 inputs. The SYNC pattern is
composed of six ones and six zeros switching at the input clock rate.
The Deserializer LOCK output will remain high while its PLL is locking to the local clock- the REFCLK input and
then to SYNC patterns on the input.
Step 2: The Deserializer PLL must synchronize to the Serializer to complete the initialization. The transmission of
SYNC patterns to the Deserializer enables the Deserializer to lock to the Serializer signal.
Control of the sync pins is left to the user. A feedback loop between the LOCK pin is one recommendation.
Another option is that one or both of the Serializer SYNC inputs are asserted for at least 1024 cycles of TCLK to
initiate transmission of SYNC patterns. The Serializer will continue to send SYNC patterns after the minimum of
1024 if either of the SYNC inputs remain high.
When the Deserializer detects edge transitions at the Bus LVDS input it will attempt to lock to the embedded
clock information. When the Deserializer locks to the Bus LVDS clock, the LOCK output will go low. When LOCK
is low the Deserializer outputs represent incoming Bus LVDS data.
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